A converter operable to convert an input voltage at an input node to an output voltage at an output node coupled to a load by switching on and off a transistor at a switching frequency, the converter comprising: an error amplifier circuit having a first input coupled to a reference voltage, a second input coupled to the output node through a resistive divider, a first output operable to output a control current and a second output operable to output a current equivalent to the control current; a peak current comparator circuit having a first input coupled to the second output of the error amplifier circuit, a second input and an output, the second input is coupled to the input node through an inductor; an off-time timer circuit having an input coupled to the first output of the error amplifier circuit and an output, the off-time timer circuit operable to set the switching frequency based on the control current; and a control circuit having a first input coupled to the output of the peak current comparator circuit, a second input coupled to the output of the off-time timer circuit and an output coupled to a control terminal of the transistor.

A supply-glitch-tolerant voltage regulator includes a regulated voltage node and an output transistor having a source terminal, a gate terminal, and a drain terminal. The source terminal is coupled to the regulated voltage node. The supply-glitch-tolerant voltage regulator includes a first current generator coupled between a first node and a first power supply node. The supply-glitch-tolerant voltage regulator includes a second current generator coupled between the first node and a second power supply node. The supply-glitch-tolerant voltage regulator includes a feedback circuit coupled to the first current generator and the second current generator and is configured to adjust a voltage on the first node based on a reference voltage and a voltage level on the regulated voltage node. The supply-glitch-tolerant voltage regulator includes a diode coupled between the drain terminal and the first power supply node and a resistor coupled between the gate terminal and the first node.

An image sensing device and an operating method thereof. The image sensing device includes a ramp signal generation circuit suitable for generating a ramp signal which corresponds to an analog gain, based on a main bias voltage, a cascode bias voltage and a plurality of ramp code signals, a bias voltage generation circuit suitable for generating the main bias voltage and the cascode bias voltage according to the analog gain, and a boost circuit suitable for boosting an output terminal of the cascode bias voltage according to the analog gain.

Methods and apparatus for adaptively generating a reference voltage (V.sub.REF) for biasing a switch driver and corresponding switch in a digital-to-analog converter (DAC). The adaptive biasing scheme may be capable of tracking process, voltage, and temperature (PVT) of the DAC. An example DAC generally includes a plurality of DAC cells, each DAC cell comprising a current source, a switch coupled in series with the current source, and a switch driver coupled to a control input of the switch, the switch driver being configured to receive power from a first power supply rail referenced to a reference potential node; a regulation circuit comprising a first transistor coupled between the reference potential node for the DAC and the switch driver in at least one of the plurality of DAC cells; and a V.sub.REF generation circuit coupled to the regulation circuit and configured to adaptively generate a V.sub.REF for the regulation circuit.

Methods, systems, and devices for apparatus for differential memory cells are described. An apparatus may include a pair of memory cells comprising a first memory cell and a second memory cell, a word line coupled with the pair of memory cells and a plate line coupled with the pair of memory cells. The apparatus may further include a first digit line coupled with the first memory cell and a sense amplifier and a second digit line coupled with the second memory cell and the sense amplifier. The apparatus may include a select line configured to couple the first digit line and the second digit line with the sense amplifier.

According to one embodiment, a constant voltage circuit includes: a first gain stage configured to output a first voltage amplified based on an output voltage and a reference voltage; a first transistor configured to control the output voltage based on the first voltage applied to a gate; and a second circuit configured to control a first signal based on a second voltage obtained by delaying an output timing of the output voltage and a third voltage that is based on the output voltage. In a case of the first signal being at a first logic level, a first current flows through the first gain stage, and in a case of the first signal being at a second logic level, a second current flows through the first gain stage.

An operational amplifier operates upon receiving supply of a first voltage and outputs a control voltage on the basis of a reference voltage. A first output transistor has a first electrode connected to a first voltage line that is a supply line for the first voltage; the first output transistor transmits a first current on the basis of the control voltage. An overcurrent protection circuit is connected to the operational amplifier, and includes a resistance unit for adjustment of a temperature coefficient.

Systems and circuits include an amplifier having an output; a switching circuit coupled to the output of the amplifier to provide a bias current to bias the amplifier; first current generating circuitry coupled to the switching circuit; and second current generating circuitry coupled to the output of the amplifier and to the switching circuit. In operation, the switching circuit provides the bias current, during a first time period, in response to a first signal generated by the first current generating circuitry, and provides the bias current, during a second time period, after the first time period, in response to a second signal generated by the second current generating circuitry.

In examples, an apparatus includes a FET, first and second voltage-to-current circuits, a current selection circuit, and a comparator. The FET has first and second segments. The first segment has a first gate coupled to the first voltage-to-current circuit, a first source, and a first drain. The second segment has a second gate coupled to the second voltage-to-current circuit, a second source coupled to the first source, and a second drain coupled to the first drain. The current selection circuit has a current selection circuit output and first and second current selection inputs. The first current selection circuit input is coupled to the first voltage-to-current circuit. The second current selection circuit input is coupled to the second voltage-to-current circuit. The comparator has a comparator output and first and second comparator inputs, the first comparator input is coupled to the current selection circuit output.

The present disclosure relates to circuitry comprising: digital circuitry configured to generate a digital output signal; and monitoring circuitry configured to monitor a supply voltage to the digital circuitry and to output a control signal for controlling operation of the digital circuitry, wherein the control signal is based on the supply voltage.