Systems and methods as described herein may take a variety of forms. In one example, systems and methods are provided for a circuit for powering a voltage regulator. A voltage regulator circuit has an output electrically coupled to a gate of an output driver transistor, the output driver transistor having a first terminal electrically coupled to a voltage source and a second terminal electrically coupled to a first terminal of a voltage divider, the voltage divider having an second terminal electrically coupled to ground, and the voltage divider having an output of a stepped down voltage. A power control circuitry transistor has a first terminal electrically coupled to the voltage source, the power control circuitry transistor having a second terminal electrically coupled to the gate terminal of the output driver transistor, and the power control circuitry transistor having a gate terminal electrically coupled to a status voltage signal.

An integrated circuit includes a first bandgap voltage reference sub-circuit configured to provide a first bandgap reference voltage; a second bandgap voltage reference sub-circuit configured to provide a second bandgap reference voltage; a voltage regulator sub-circuit configured to derive a first supply voltage using the first bandgap reference voltage and a second supply voltage using the second bandgap reference voltage; a bandgap comparator sub-circuit configured to derive a first internal voltage and a second internal voltage from the first supply voltage, wherein the first internal voltage decreases at a higher rate than the second internal voltage with respect to a decreasing first supply voltage, wherein the bandgap comparator sub-circuit is configured indicate which of the first and the second internal voltages is larger; and a comparator sub-circuit configured to indicate whether a difference between the first supply voltage and the second supply voltage is larger than a predefined threshold.

An integrated circuit includes a first bandgap voltage reference sub-circuit configured to provide a first bandgap reference voltage; a second bandgap voltage reference sub-circuit configured to provide a second bandgap reference voltage; a voltage regulator sub-circuit configured to derive a first supply voltage using the first bandgap reference voltage and a second supply voltage using the second bandgap reference voltage; a bandgap comparator sub-circuit configured to derive a first internal voltage and a second internal voltage from the first supply voltage, wherein the first internal voltage decreases at a higher rate than the second internal voltage with respect to a decreasing first supply voltage, wherein the bandgap comparator sub-circuit is configured indicate which of the first and the second internal voltages is larger; and a comparator sub-circuit configured to indicate whether a difference between the first supply voltage and the second supply voltage is larger than a predefined threshold.

A reference voltage circuit includes: a first and a second NPN transistor having a collector and a base shorted and diode-connected, the second NPN transistor having an emitter connected to a first potential node and operating at a higher current density; a first resistor connected in series with the first NPN transistor; a second resistor having one end connected to a circuit with the first NPN transistor and the first resistor connected in series; a third resistor having one end connected to the collector of the second NPN transistor; a connection point to which the other ends of the second and the third resistor are connected; an arithmetic amplifier circuit having an inverting input terminal, a non-inverting input terminal, and an output terminal respectively connected to the second resistor, the third resistor, and the connection point; and a current supply circuit connected to the collector of the first NPN transistor.

A reference voltage circuit includes: a first and a second NPN transistor having a collector and a base shorted and diode-connected, the second NPN transistor having an emitter connected to a first potential node and operating at a higher current density; a first resistor connected in series with the first NPN transistor; a second resistor having one end connected to a circuit with the first NPN transistor and the first resistor connected in series; a third resistor having one end connected to the collector of the second NPN transistor; a connection point to which the other ends of the second and the third resistor are connected; an arithmetic amplifier circuit having an inverting input terminal, a non-inverting input terminal, and an output terminal respectively connected to the second resistor, the third resistor, and the connection point; and a current supply circuit connected to the collector of the first NPN transistor.

A curvature compensated bandgap circuit that is capable of matching best-in-class two (2) parts-per-million performance without over-temperature trimming. This improves performance metrics for precision voltage reference products without requiring individual device tuning during production thereof. A core bandgap circuit comprises a main operational amplifier having a second order bowed voltage response over temperature. A ptat circuit is coupled to the core bandgap circuit to provide a sigmoidal third order shape for the bandgap voltage.

A curvature compensated bandgap circuit that is capable of matching best-in-class two (2) parts-per-million performance without over-temperature trimming. This improves performance metrics for precision voltage reference products without requiring individual device tuning during production thereof. A core bandgap circuit comprises a main operational amplifier having a second order bowed voltage response over temperature. A ptat circuit is coupled to the core bandgap circuit to provide a sigmoidal third order shape for the bandgap voltage.

Reference circuits are described. In particular reference circuits that use a plurality of cascaded proportional to absolute temperature, PTAT, cells are described. In the circuits disclosed, currents of the low current density arm of first PTAT cell are mirrored into the high current density arms of a second PTAT cell such that any deviation of current in the low current density arm of the first cell will be replicated as the current in the high current density arm of the second cell. In this way low noise circuits can be provided.

Reference circuits are described. In particular reference circuits that use a plurality of cascaded proportional to absolute temperature, PTAT, cells are described. In the circuits disclosed, currents of the low current density arm of first PTAT cell are mirrored into the high current density arms of a second PTAT cell such that any deviation of current in the low current density arm of the first cell will be replicated as the current in the high current density arm of the second cell. In this way low noise circuits can be provided.

A reference voltage circuit includes a first circuit including a first PN junction device and a first resistor connected in series between a power supply node and a first node, and a second resistor connected between the first node and an intermediate node, and a third resistor connected between the intermediate node and a reference voltage output node, and a second circuit including a second PN junction device connected between the power supply node and a second node and a fourth resistor connected between the second node and the intermediate node. A feedback current causes voltage across the first resistor to offset changes in voltage across the first PN junction device. A correction current is applied to boost and or sink current in the voltage reference generator to extend the operating temperature range.