An information processing apparatus includes a memory and a processor coupled to the memory. The processor is configured to calculate, for each of first users, time lengths of accesses to data stored in a storage device on basis of start information on start times and finish information on finish times. The accesses are made by a node of each of the first users. The start times are times at which the respective accesses are started. The finish times are times at which the respective accesses are finished. The processor is configured to calculate, for each of second users among the first users, a first sum of the time lengths. The second users are in a logged-in state of being after login and before logout. The processor is configured to determine whether to power on the storage device on basis of the first sum.

A solid-state drive and a performance optimization method for the solid-state drive are provided. The performance optimization method for the solid-state drive includes the following steps: detecting a queue depth of the solid-state drive to determine a use proportion of the queue depth; determining whether an access speed of the solid-state drive is raisable when the use proportion of the queue depth is higher than a first threshold proportion, so as to raise the access speed of the solid-state drive; and determining whether the access speed of the solid-state drive is reduceable when the use proportion of the queue depth is lower than a second threshold proportion, so as to reduce the access speed of the solid-state drive.

A method for adjusting a voltage of a supercapacitor is disclosed, the method, which is used to retard aging of the supercapacitor and extend a service life of the supercapacitor, includes: acquiring information that carries a system service volume; configuring a size of an available capacity value of the Cache according to the information; and adjusting a working voltage of the supercapacitor according to the configured size of the available capacity value of the Cache.

According to one embodiment, a memory device includes a second memory and a controller circuit. Power supply to the memory device is stopped in a second state. Internal data of the controller circuit is saved in a first memory of a host device in the second state. The controller circuit acquires information indicating resuming from the second state from the host device to perform a process of making the memory device transition from the second state to the first state.

A method and apparatus of a device that manages system performance by controlling power state based on information related to I/O operations is described. The device collects historical I/O information. The historical I/O information may include the number of I/O operations over a sample period of time and the inter-arrival time between I/O operations. The device further receives information related to a current I/O operation. The information of the current I/O operation may include direction, size, quality of service, and media type of the I/O operation. The device determines a power state based on the historical I/O information and the information relative to the current I/O operation to reduce power consumption while improving system efficiency and maintaining an acceptable level of system performance. The device further applies the determined power state. Other embodiments are also described and claimed.

A method and apparatus of a device that manages system performance by controlling power state based on information related to I/O operations is described. The device collects historical I/O information. The historical I/O information may include the number of I/O operations over a sample period of time and the inter-arrival time between I/O operations. The device further receives information related to a current I/O operation. The information of the current I/O operation may include direction, size, quality of service, and media type of the I/O operation. The device determines a power state based on the historical I/O information and the information relative to the current I/O operation to reduce power consumption while improving system efficiency and maintaining an acceptable level of system performance. The device further applies the determined power state. Other embodiments are also described and claimed.

The present disclosure relates to systems and methods for power outage protection. The system may obtain a read/write signal of each of a plurality of storage devices. For each of the plurality of storage devices, the system may identify a state of the storage device based on the read/write signal of the storage device. The state of the storage device may include a read/write state or an idle state of the storage device. In response to an interruption of power supply to the plurality of storage devices, the system may selectively provide electric power to the plurality of storage devices using a power source based at least partially on the states of the plurality of storage devices.

Systems and methods, according to the present disclosure, determines a duration of the current queue of commands in the controller, executes all full commands capable of being executed prior to the beginning of a low power cycle. Commands that are not executed may be re-fetched when the device enters a power mode. In an alternate embodiment, a portion of a command that is executable prior to the beginning of a low power cycle is executed, with the un-executed portion of the command being stored on the device, in an “always on” or AON memory. This un-executed portion is fetched and executed when the device enters the power mode.

Aspects of a storage device are provided which delay thermal throttling in response to temperature increases based on different reliable temperatures for different types of cells, such as SLCs, hybrid SLCs and MLCs. Initially, a controller writes first data to a block of MLCs at a first data rate when a temperature of the block meets a first temperature threshold for MLCs. Subsequently, the controller writes second data to the block at a second data rate lower than the first data rate when the temperature of the block meets a second temperature threshold for SLCs. For hybrid SLCs, the MLCs are each configured to store a first number of bits, and the controller writes a second number of bits smaller than the first number of bits in each of one or more of the cells. Storage device performance is thus improved through delayed thermal throttling without compromising data integrity.

Examples described herein relate to circuitry to cause a processor to enter reduced power consumption state and circuitry to, based on a write to one or more of multiple memory regions, cause the processor to exit reduced power consumption state, wherein the multiple memory regions store receive descriptors associated with one or more packets received by a network interface device. In some examples, multiple memory regions are defined by a driver of the network interface device. In some examples, the reduced power consumption state comprises a TPAUSE state.