A circuit comprises a power controller, a real-time clock (RTC) sub-system, and a processing sub-system. The RTC sub-system includes an alarm register storing a predetermined time for a task, and provides an early warning countdown and a scheduled event signal. The processing sub-system includes a processor, a preemptive wakeup circuit, and a component coupled to the processor and configured to execute the task with the processor. The preemptive wakeup circuit comprises a selector logic circuit, a comparator, and a wakeup initiation circuit. The selector logic circuit receives latency values indicative of wakeup times for a clock generator and the component, and outputs a longest wakeup time to the comparator, which indicates when the early warning countdown and the longest wakeup time are equal. The wakeup initiation circuit generates a clock request and disables the sleep mode indicator. The power controller provides a clock signal and wakes the component.

An electronic device has a memory functional block that includes memory circuits and a memory physical layer (PHY) functional block with core logic that controls operations in the memory functional block, a memory PHY voltage regulator, a system voltage regulator, and a controller. The electronic device also includes a switch having an input coupled to an output of the memory PHY voltage regulator, another input coupled to an output of the system voltage regulator, and an output coupled to a power supply input of the core logic. The controller sets the switch so that electrical power is provided from the memory PHY voltage regulator to the core logic in a full power operating state. The controller sets the switch so that electrical power is provided from the system voltage regulator to the core logic in one or more low power operating states.

The invention introduces a non-transitory computer-readable storage medium for adjusting operating frequencies when executed by a processing unit of a device, containing program code to: collect an interface-activity parameter comprising information about data transmissions on a host access interface and/or a flash access interface; select one from multiple frequencies according to the interface-activity parameter; and drive a clock generator to output a clock signal at the selected frequency, thereby enabling the host access interface and/or the flash access interface to operate at an operating frequency.

The invention introduces a non-transitory computer-readable storage medium for adjusting operating frequencies when executed by a processing unit of a device, containing program code to: collect an interface-activity parameter comprising information about data transmissions on a host access interface and/or a flash access interface; select one from multiple frequencies according to the interface-activity parameter; and drive a clock generator to output a clock signal at the selected frequency, thereby enabling the host access interface and/or the flash access interface to operate at an operating frequency.

There are provided a sensor data collection device, a sensor data collection system, and a method of collecting sensor data capable of reducing a drain of a battery due to standby power. The sensor data collection device includes a power supply, a power supply control circuit configured to control the power supply, a sensor configured to perform sensing to thereby obtain data, a memory configured to store the data obtained by the sensor, and a control circuit configured to control the power supply control circuit, the sensor, and the memory. The power supply control circuit supplies the sensor, the memory, and the control circuit with electrical power supplied by the power supply, and the control circuit makes the transition to any one of a plurality of operating states, and makes the power supply control circuit shut off the electrical power supplied by the power supply after a first operating state is completed and before the transition to a second operating state is made wherein the first operating state and the second operating state are included in the plurality of operating states.

There are provided a sensor data collection device, a sensor data collection system, and a method of collecting sensor data capable of reducing a drain of a battery due to standby power. The sensor data collection device includes a power supply, a power supply control circuit configured to control the power supply, a sensor configured to perform sensing to thereby obtain data, a memory configured to store the data obtained by the sensor, and a control circuit configured to control the power supply control circuit, the sensor, and the memory. The power supply control circuit supplies the sensor, the memory, and the control circuit with electrical power supplied by the power supply, and the control circuit makes the transition to any one of a plurality of operating states, and makes the power supply control circuit shut off the electrical power supplied by the power supply after a first operating state is completed and before the transition to a second operating state is made wherein the first operating state and the second operating state are included in the plurality of operating states.

A storage unit is disclosed. The storage unit may include an interface to a host and storage for a data. A receiver may receive from a host a boot power data. The boot power data may including a first power level and a duration. A circuit may boot the storage unit based at least in part on the boot power data. The storage unit may include a second power level, with the first power level greater than the second power level.

Methods, systems, and devices for memory device operation are described. A memory device may operate in different modes in response to various conditions and user constraints. Such modes may include a power-saving or low power mode. While in the low power mode, the memory device may refrain from operations, such as self-refresh operations, on one or more of the memory array(s) included in the memory device. The memory device may deactivate external interface components and components that may generate operating voltages for the memory array(s), while the memory device may continue to power circuits that store operating information for the memory device. The memory device may employ similar techniques in other operating modes to accommodate or react to different conditions or user constraints.

Methods, systems, and devices for memory device operation are described. A memory device may operate in different modes in response to various conditions and user constraints. Such modes may include a power-saving or low power mode. While in the low power mode, the memory device may refrain from operations, such as self-refresh operations, on one or more of the memory array(s) included in the memory device. The memory device may deactivate external interface components and components that may generate operating voltages for the memory array(s), while the memory device may continue to power circuits that store operating information for the memory device. The memory device may employ similar techniques in other operating modes to accommodate or react to different conditions or user constraints.

The various embodiments disclose an electronic device including: a storage including a non-volatile memory having a buffer space and a storage space, a storage device controller, and a storage interface, and a processor. According to various embodiments, the processor may be configured to perform control to determine whether the storage supports a high speed data storage mode using a buffer space of a non-volatile memory of the storage, activate a function of writing data buffered in the buffer space of the non-volatile memory into a storage space of the non-volatile memory based on the storage interface operating in a first state based on the storage supporting the high speed data storage mode, and transition the storage interface of the storage to the first state based on no request to the storage being generated during a predetermined time period based on the storage interface operating in a second state.