An information handling system includes a plurality of containerized applications, a container service, a hardware device, and a host processor to initialize a host service. The container service is associated with the containerized applications. The hardware device is virtualized to the containerized applications. The host processor identifies the hardware device that is virtualized to the containerized applications. The host processor receives a power notification from the container service. Based on the power notification, the host processor changes a power state of the hardware device.

Power-saving techniques in computing devices through communication bus control start a timer when data is ready to be sent across a communication bus from a first terminus to a second terminus. While the timer is running, any data from any channel that is ready to be sent across the communication bus from the first terminus to the second terminus is accumulated. At expiration of the timer, all data is sent across the communication bus. By holding or accumulating the data in this fashion, unnecessary transitions between low-power states and active states on the communication bus are reduced and power is conserved. The timer may be set based on latency requirements of the data ready to be sent.

Methods and apparatus to permit a system low power consumption state when CPU (Central Processing Unit) or generically any compute element is active are described. In an embodiment, a fabric and a memory controller are caused to enter a low power consumption state at least partially in response to a determination that the fabric and the memory controller are idle. The entry into the low power consumption state occurs while a compute element, coupled to the fabric and the memory controller, is in an active state. Other embodiments are also disclosed and claimed.

An apparatus and method for reducing power consumption in a portable terminal are provided. The apparatus includes a display unit for displaying at least one indicator that indicates status information measured by a slave processor, a master processor for controlling one of ON and OFF of the display unit and for providing image data to the display unit, and the slave processor for transmitting to the master processor indicator update information for updating the at least one indicator, wherein transmission to the master processor of the indicator update information is discontinued if the status of the display unit is OFF.

Power saving systems and methods for Universal Serial Bus (USB) systems are disclosed. When a USB physical layer (PHY) enters a U3 low power state, not only are normal elements powered down, but also circuitry within the USB PHY associated with detection of a low frequency periodic signal (LFPS) wake up signal is powered down. A low speed reference clock signal is still received by the USB PHY, and a medium speed clock within the USB PHY is activated once per period of the low speed reference clock signal. The medium speed clock activates the signal detection circuitry and samples a line for the LFPS. If no LFPS is detected, the signal detection circuitry and the medium speed clock return to low power until the next period of the low speed reference clock signal. If the LFPS is detected, the USB PHY returns to a U0 active power state.

In an embodiment, a processor includes at least one core and an interconnect that couples the at least one core and the cache memory. The interconnect is to operate at an interconnect frequency (f.sub.CL). The processor also includes a power management unit (PMU) including f.sub.CL logic to determine whether to adjust the f.sub.CL responsive to a Bayesian prediction value that is associated with scalability of a workload to be processed by the processor. The Bayesian prediction value may be determined based on one or more activity measures associated with the processor. Other embodiments are described and claimed.

A semiconductor device can reduce power consumption in a low power mode and includes a first input/output circuit configured to detect a first entry signal transiting at a first time and output a detection signal indicating an entry into a power saving mode according to a result of the detection. A second input/output circuit is configured to receive a second entry signal transiting at a second time earlier than the first time, and a control circuit is configured to block power supplied to the second input/output circuit in response to the detection signal indicating the entry.

An apparatus includes a first node configured to provide a first supply voltage to a first device and a second node configured to provide a second supply voltage to a second device. The apparatus further includes a bus configured to communicatively couple the first device and the second device. The apparatus also includes a switch configured to couple the first node and the second node.

A system including a bus, a buffer, a bridge and a module. The bus is connected to multiple devices. The buffer is connected to the bus. The buffer is configured to transfer data to or receive the data from one or more of the devices, forward the data during a forwarding mode, and receive the data during a gathering mode. The module is configured to determine whether a first condition and/or a second condition exist. Based on whether the first condition exists, the module is configures the bridge to transfer the data from the buffer to a host system or transitions the buffer from the gathering mode to the forwarding mode to forward the data from the buffer to the one or more of the devices. Based on whether the second condition exists, the module is configured to transition the buffer from the forwarding mode to the gathering mode.

A computer-implemented method for controlling power consumption in a non-volatile dual inline memory module (NVDIMM-N) may include determining, via a processor, whether the NVDIMM-N is receiving power from a main power source, inactivating, via the processor, a data bus connected to an NVDIMM-N memory group responsive to determining that the NVDIMM-N is not receiving power from the main power source, backing up data stored in the NVDIMM-N memory group, via the processor, to a non-volatile memory module integrated with the NVDIMM-N, where an NVDIMM-N controller can access the NVDIMM-N memory group while backing up, and transmitting, via the processor, a low power command to an NVDIMM-N controller to place the NVDIMM-N memory group in a low power mode.