A multi-element device includes a plurality of memory elements, each of which includes a memory array, access circuitry to control access to the memory array, and power control circuitry. The power control circuitry, which includes one or more control registers for storing first and second control values, controls distribution of power to the access circuitry in accordance with the first control value, and controls distribution of power to the memory array in accordance with the second control value. Each memory element also includes sideband circuitry for enabling a host system to set at least the first control value and the second control value in the one or more control registers.

Methods, systems, and devices for a dynamic interval for entering a low power state are described. A memory system or device may support a low power mode, which the memory system or device may enter in response to a command from a host system. In some cases, an amount of idle time observed by the host system before issuing such a command may vary based on a status of maintenance operations for the memory system or device. Additionally or alternatively, after receiving such a command, the memory system or device may complete one or more pending maintenance operations before entering the low power mode.

Methods, systems, and devices for dynamic power control are described. In some examples, a memory device may be configured to adjust a first duration for transitioning power modes. For example, the memory device may be configured to operate in a first power mode, a second power mode, and a third power mode. When operating in a second power mode, the memory device may be configured to increase or decrease the first duration for transitioning to a third power mode based on a second duration between received commands. If no commands are received during the first duration, the memory device may transition from the second power mode to the third power mode.

A method and apparatus for identifying data that is to be accessible in a low power state of a data storage device, and store this data in a physical (or logical) block that will be accessible in a low power state of the data storage device. Low power accessible data may be identified by host metadata of the data, indicating access is needed in a low power state. In other embodiments, the data storage device may learn the power state in which data should be accessible. In these embodiments, a controller stores information regarding the power state of a namespace in which the data is stored as an indicator to make the data accessible in a low power state. Alternatively, the controller stores a previous power state in which the data was accessed as an indicator to make the data accessible in a low power state.

Apparatus, assemblies, and platforms employing modular power voltage regulator (VR) modules to provide power to memory modules. A power VR module includes VR circuitry integrated on or coupled to a substrate with wiring coupling the VR circuitry to connector elements in first and second connector means. An assembly further includes a pair of memory modules (e.g., DDR) that are coupled to a power VR module via mating connector means. The connector means may be coupled using a Compression Mount Technology (CMT) connector disposed between arrays of CMT contact pads on the power VR module and the memory modules, or may comprise BGAs, PGAs, and LGAs. The power VR module receives one or more input voltages via one or both memory module and provide various output voltages to each of the memory modules to power memory devices and other circuitry on those modules.

A data storage device and method for low-latency power state transitions by having power islanding in a host memory buffer are provided. In one embodiment, a data storage device is provided comprising a volatile memory, a non-volatile memory, and a controller. The controller is configured to receive information from a host about which area, if any, in a host memory buffer will be powered on during a low-power state; and in response to the information indicating that a first area of the host memory buffer will be powered on during the low-power state, flush data from a second area of the host memory buffer that will not be powered on during the low-power state to the first area of the host memory buffer prior to entering the low-power state. Other embodiments are provided.

Disclosed is an electronic device. The electronic device may include a plurality of interfaces each of which is connected to one peripheral electronic device in a wired manner to deliver power to the connected peripheral electronic device, a power supply circuit connected to the plurality of interfaces, and a control circuit including a plurality of pins each connected to one interface to allow the power supply circuit to supply power to the plurality of interfaces. In addition, various embodiments understood from the disclosure are possible.

A processor system and method is described. The processor system includes a central processing unit (CPU) comprising a register for storing a stack pointer value, a non-volatile memory coupled to the CPU and having a first non-volatile memory region configured to store instructions executable by the CPU and a second non-volatile memory region configured to store a RAM-image comprising program context data. The processor system includes a random-access memory (RAM) coupled to the CPU and having a first RAM region and a second RAM region. The processor system is configured to have a first operating mode where the RAM data values are not retained and a second operating mode where the RAM is powered on. In operation, the processor system changes from the first operating mode to the second operating mode by applying power to the RAM, setting the stack pointer value to an address in the second RAM region, copying the program context data from the second non-volatile memory region to the first RAM region, and setting the stack pointer value to an address within a segment of the first RAM region.

Logical memory is divided into two regions. Data in the first region is always retained. The first region of memory is designated online (or powered on) and is not offlined during standby or low power mode. The second region is the rest of the memory which can be potentially placed in non-self-refresh mode during standby by offlining the memory region. Content in the second region can be moved to the first region or can be flushed to another memory managed by the operating system. When the first region does not have enough space to accommodate data from the second region, the operating system can increase the logical size of the first region. Retaining the content of the first region by putting that region in self-refresh and saving power in the second region by not putting it in self-refresh is performed by an improved Partial Array Self Refresh scheme.

A semiconductor device includes a clock gating circuit and a control circuit. The clock gating circuit outputs a gated clock signal based on a clock signal. Transitions of the clock signal are output in the gated clock signal in response to a clock enable signal having an enable value and are disabled from being output in the gated clock signal in response to the clock enable signal having a disable value. The control circuit includes a first portion that operates based on the clock signal. The first portion sets the clock enable signal to the disable value in response to a disable control and sets the clock enable signal to the enable value in response to a wakeup control. The control circuit includes a second portion that operates based on the gated clock signal. The second portion provides the disable control to the first portion during an operation.