Disclosed is a sideband signal adjustment system including an M.2 interface module containing a first power supply voltage pin and a second power supply voltage pin, a switching module, and a control module. When the control module detects that the second power pin receives a second power voltage, the switching module electrically connects to the second power supply voltage pin, and the control module receives or sends a second sideband signal with the same voltage level as the second power supply voltage through the M.2 interface module. When the control module detects that the first power supply voltage pin receives the first power supply voltage different from the second power voltage, the switching module electrically connects to the first power supply voltage pin, and the control module receives or sends a first sideband signal with the same voltage level as the first power supply voltage through the M.2 interface module.

A computer system comprising a scheduled computation module, a work memory storage device, and a controller. The scheduled computation module is configured to receive and process data values according to a predetermined access pattern. The work memory storage device includes one or more work memory banks. The controller is configured to, based on scheduling information associated with the predetermined access pattern, (1) provide data values held by the one or more work memory banks to the scheduled computation module, and (2) selectively control a power state of the one or more work memory banks.

Systems and methods are disclosed for data storage performance scaling based on external energy. In certain embodiments, a system may comprise a data storage device having an interface to communicate with an external device, a nonvolatile memory, and a circuit. The circuit may be configured to receive an indication via the interface of power resources available to the data storage device from the external device in case of a power loss event, adjust a performance metric of the data storage device to apply when accessing the nonvolatile memory during normal power availability based on the indication, and perform operations during normal power availability based on the performance metric.

Systems and methods for discrete power control of components within a computer system are described herein. Some illustrative embodiments include a system that includes a subsystem with a plurality of components (configurable to operate at one or more power levels), a control register (coupled to the plurality of components) including a plurality of bits (each uniquely associated with a one of the plurality of components), and a power controller coupled to, and configurable to cause, the plurality of components to operate at the one or more power levels. The power controller asserts a signal transmitted to the subsystem, commanding the subsystem to transition to a first power level. A first of the plurality of components, associated with an asserted bit of the control register, operates at a second power level corresponding to a level of power consumption different from that of the first power level indicated by the power controller.

A storage device includes a solid state drive (SSD), a field programmable gate array (FPGA), a power sensor and a global controller. The SSD stores data and receives power through a power rail connected to a host device. The FPGA processes data read from the SSD or data to be stored in the SSD and receives power through the power rail. The power sensor is connected to the power rail and generates a measured power value corresponding to a total power consumed by the SSD and the FPGA by measuring the total power. The global controller determines one of the SSD and the FPGA as a priority component operating with a fixed performance and determines the other of the SSD and the FPGA as a non-priority component operating with a variable performance in a priority mode based on power control information provided from the host device.

Exemplary methods, apparatuses, and systems include a media temperature manager receiving operating temperature measurements for a memory subsystem. The media temperature manager generates an average temperature using the operating temperature measurements. The media temperature manager determines that the average temperature satisfies a first value for a dynamic temperature threshold. The dynamic temperature threshold indicates a temperature at which the memory subsystem throttles media operations. The media temperature manager increases the dynamic temperature threshold to a second value in response to the average temperature satisfying the first value for the dynamic temperature threshold.

A set of read operations and a set of write operations for a set of drives in a storage system during a first time window is monitored. A write intensity of a first drive in the set is calculated based on the monitoring. The first drive is classified as a candidate for power reduction based on the write intensity. A write-intensive extent is identified on the first drive based on the monitoring. The write extensive extent is migrated to a second drive in the set of drives, and power to the first drive is reduced.

A processor sets the size of a processor cache based on an identified workload executing at the processor. The cache size is set in response to the processor exiting a low-power mode. By setting the size of the cache based on the workload, the processor is able to tailor the size of the cache to the characteristics of a particular workload while also reducing, for at least some workloads, the overhead associated with entering or exiting the low-power mode.

Apparatuses, systems and methods for performing efficient power management for a processing unit. A processing unit includes two partitions, each assigned to a respective power domain with operating parameters, and each with a respective direct memory access

(DMA) engine. If a controller determines a task type of a received task indicates the task is to be processed by components of the second partition, then the controller assigns the task to the second partition and maintains the operational parameters of the first power domain for the components of the first partition or selects lower performance operational parameters of the first power domain. The processing unit accesses data stored in memory using a DMA engine and operational parameters of the second partition. Additionally, the second partition processes the task using the operational parameters of the second power domain.

Systems and methods are disclosed for reducing the power consumption of a system. Techniques are described that queue a message, sent by a source engine of the system, in a queue of a destination engine of the system that is in a sleep mode. Then, a priority level associated with the queued message is determined. If the priority level is at a maximum level, the destination engine is brought into an active mode. If the priority level is at an intermediate level, the destination engine is brought into an active mode when a time, associated with the intermediate level, has elapsed. When the destination engine is brought into an active mode it processes all messages accumulated in its queue in an order determined by their associated priority levels.