Methods and apparatuses for PDCCH reception and transmission. A method for PDCCH reception includes transmitting a capability for receptions of PDCCHs on a downlink (DL) cell. PDCCH receptions on the DL cell are according to (X.sub.1, Y.sub.1) or (X.sub.2, Y.sub.2) when any two PDCCH receptions are within Y.sub.1 or Y.sub.2 symbols or have first symbols separated by at least X.sub.1 or X.sub.2 symbols, respectively. The method further includes receiving a configuration of search space sets for PDCCH receptions on the DL cell; determining, based on the configuration of the search space sets, whether PDCCH receptions are according to (X.sub.2, Y.sub.2); and receiving on the DL cell: a maximum number of M.sub.PDCCH.sup.max,X.sup.1.sup.,? PDCCHs within Y.sub.1 symbols when PDCCH receptions are not according to (X.sub.2, Y.sub.2), and a maximum number of M.sub.PDCCH.sup.max,X.sup.2.sup.,? PDCCHs within Y.sub.2 symbols when PDCCH receptions are according to (X.sub.2, Y.sub.2).

A round-for-reround mode (preferably in a BID encoded Decimal format) of a floating point instruction prepares a result for later rounding to a variable number of digits by detecting that the least significant digit may be a 0, and if so changing it to 1 when the trailing digits are not all 0. A subsequent reround instruction is then able to round the result to any number of digits at least 2 fewer than the number of digits of the result. An optional embodiment saves a tag indicating the fact that the low order digit of the result is 0 or 5 if the trailing bits are non-zero in a tag field rather than modify the result. Another optional embodiment also saves a half-way-and-above indicator when the trailing digits represent a decimal with a most significant digit having a value of 5. An optional subsequent reround instruction is able to round the result to any number of digits fewer or equal to the number of digits of the result using the saved tags.

Methods and apparatuses for PDCCH reception and transmission. A method for PDCCH reception includes transmitting a capability for receptions of PDCCHs on a downlink (DL) cell. PDCCH receptions on the DL cell are according to (X.sub.1, Y.sub.1) or (X.sub.2, Y.sub.2) when any two PDCCH receptions are within Y.sub.1 or Y.sub.2 symbols or have first symbols separated by at least X.sub.1 or X.sub.2 symbols, respectively. The method further includes receiving a configuration of search space sets for PDCCH receptions on the DL cell; determining, based on the configuration of the search space sets, whether PDCCH receptions are according to (X.sub.2, Y.sub.2); and receiving on the DL cell: a maximum number of M.sub.PDCCH.sup.max,X.sup.1.sup., PDCCHs within Y.sub.1 symbols when PDCCH receptions are not according to (X.sub.2, Y.sub.2), and a maximum number of M.sub.PDCCH.sup.max,X.sup.2.sup., PDCCHs within Y.sub.2 symbols when PDCCH receptions are according to (X.sub.2, Y.sub.2).

A round-for-reround mode (preferably in a BID encoded Decimal format) of a floating point instruction prepares a result for later rounding to a variable number of digits by detecting that the least significant digit may be a 0, and if so changing it to 1 when the trailing digits are not all 0. A subsequent reround instruction is then able to round the result to any number of digits at least 2 fewer than the number of digits of the result. An optional embodiment saves a tag indicating the fact that the low order digit of the result is 0 or 5 if the trailing bits are non-zero in a tag field rather than modify the result. Another optional embodiment also saves a half-way-and-above indicator when the trailing digits represent a decimal with a most significant digit having a value of 5. An optional subsequent reround instruction is able to round the result to any number of digits fewer or equal to the number of digits of the result using the saved tags.

An apparatus and method for generating a sum of floating-point input values are provided. To sum the values multiple partial sum floating-point values are maintained and the partial sum to which an input value may be added is selected by a least significant portion of the exponent of the input value. If the exponent of the input value is equal to the exponent of the value stored in the selected partial sum a mantissa sum of the input value and stored partial sum value replaces the mantissa value of the selected partial sum value. If the exponent of the input value is larger than the exponent of the value stored in the selected partial sum the selected partial sum value is replaced with the input value. An associative and deterministic summation is thus provided.

A round-for-reround mode (preferably in a BID encoded Decimal format) of a floating point instruction prepares a result for later rounding to a variable number of digits by detecting that the least significant digit may be a 0, and if so changing it to 1 when the trailing digits are not all 0. A subsequent reround instruction is then able to round the result to any number of digits at least 2 fewer than the number of digits of the result. An optional embodiment saves a tag indicating the fact that the low order digit of the result is 0 or 5 if the trailing bits are non-zero in a tag field rather than modify the result. Another optional embodiment also saves a half-way-and-above indicator when the trailing digits represent a decimal with a most significant digit having a value of 5. An optional subsequent reround instruction is able to round the result to any number of digits fewer or equal to the number of digits of the result using the saved tags.

A round-for-reround mode (preferably in a BID encoded Decimal format) of a floating point instruction prepares a result for later rounding to a variable number of digits by detecting that the least significant digit may be a 0, and if so changing it to 1 when the trailing digits are not all 0. A subsequent reround instruction is then able to round the result to any number of digits at least 2 fewer than the number of digits of the result. An optional embodiment saves a tag indicating the fact that the low order digit of the result is 0 or 5 if the trailing bits are non-zero in a tag field rather than modify the result. Another optional embodiment also saves a half-way-and-above indicator when the trailing digits represent a decimal with a most significant digit having a value of 5. An optional subsequent reround instruction is able to round the result to any number of digits fewer or equal to the number of digits of the result using the saved tags.

A round-for-reround mode (preferably in a BID encoded Decimal format) of a floating point instruction prepares a result for later rounding to a variable number of digits by detecting that the least significant digit may be a 0, and if so changing it to 1 when the trailing digits are not all 0. A subsequent reround instruction is then able to round the result to any number of digits at least 2 fewer than the number of digits of the result. An optional embodiment saves a tag indicating the fact that the low order digit of the result is 0 or 5 if the trailing bits are non-zero in a tag field rather than modify the result. Another optional embodiment also saves a half-way-and-above indicator when the trailing digits represent a decimal with a most significant digit having a value of 5. An optional subsequent reround instruction is able to round the result to any number of digits fewer or equal to the number of digits of the result using the saved tags.

A decimal floating-point instruction is executed in a round-for-reround mode. The decimal floating-point instruction is configured to perform a decimal floating-point operation on a decimal floating-point operand. The executing includes forming based on performing the decimal floating-point operation, an intermediate result having a high order portion and a low order portion. The high order portion has a least significant digit. A rounded-for-reround number is created from the intermediate result. The rounded-for-reround number includes the high order portion of the intermediate result and based on the least significant coefficient digit of the high order portion being a selected value and based on the low order portion having another selected value, the least significant digit of the rounded-for-reround number is incremented. The rounded-for-reround number is stored.

A normalizer for performing normalization on floating-point data includes a search circuit configured to receive selected mantissa data and to output reference exponent data and shift data, the selected mantissa data being either mantissa data of the floating-point data or 2's complement data of the mantissa data, an exponent adder configured to output normalized exponent data by adding exponent data of the floating-point data and the reference exponent data, and a unidirectional mantissa shifter configured to output normalized mantissa data by performing a unidirectional shift on the selected mantissa data based on a value of the shift data.