A device of executing a cryptographic operation on bit vectors, the execution of the cryptographic operation includes the execution of at least one arithmetic addition operation between a first operand and a second operand. Each operand comprises a set of components, each component corresponding to a given bit position of the operand. The device comprises a set of elementary adders, each elementary adder being associated with a given bit position of the operands and being configured to perform a bitwise addition between a component of the first operand at the given bit position and the corresponding component of the second operand at the given bit position using the carry generated by the computation performed by the elementary adder corresponding to the previous bit position. Each elementary adder has a sum output corresponding to the bitwise addition and a carry output, the result of the arithmetic addition operation being derived from the sum outputs provided by each elementary adder. The device is configured to apply a mask to each operand component input of at least some of the elementary adders using a masking logical operation, the mask being a random number.

A method for an associative memory device includes storing a plurality of pairs of N-bit numbers A and B to be added together in columns of a memory array of the associative memory device, each pair in a column, each bit in a row of the column, and dividing each N-bit number A and B into groups containing M bits each, having group carry-out predictions for every group except a first group, the group carry-out predictions calculated for any possible group carry-in value, and, once the carry-out value for a first group is calculated, selecting the next group carry out value from the group carry-out predictions. The method also includes repeating the ripple selecting group carry-out values, until all group carry out values have been selected.

A method for an associative memory device includes storing a plurality of pairs of N-bit numbers A and B to be added together in columns of a memory array of the associative memory device, each pair in a column, each bit in a row of the column, and dividing each N-bit number A and B into groups containing M bits each, having group carry-out predictions for every group except a first group, the group carry-out predictions calculated for any possible group carry-in value, and, once the carry-out value for a first group is calculated, selecting the next group carry out value from the group carry-out predictions. The method also includes repeating the ripple selecting group carry-out values, until all group carry out values have been selected.

A system, structure and method using radix-1000 (instead of radix-10) are implemented to represent and operate on decimal floating-point numbers. Instead of using a 10-bit declet to encode a DPD, the system, structure and method herein use a declet to encode a BCK (Binary Coded 1000 values), where the letter K is the abbreviation of the number 1000. A skewed representation of the fraction field is then used to avoid the loss of decimal digits in arithmetic operations when shifting and rounding the fraction are required.

A system, structure and method using radix-1000 (instead of radix-10) are implemented to represent and operate on decimal floating-point numbers. Instead of using a 10-bit declet to encode a DPD, the system, structure and method herein use a declet to encode a BCK (Binary Coded 1000 values), where the letter K is the abbreviation of the number 1000. A skewed representation of the fraction field is then used to avoid the loss of decimal digits in arithmetic operations when shifting and rounding the fraction are required.

A Vector Checksum instruction. Elements from a second operand are added together one-by-one to obtain a first result. The adding includes performing one or more end around carry add operations. The first result is placed in an element of a first operand of the instruction. After each addition of an element, a carry out of a chosen position of the sum, if any, is added to a selected position in an element of the first operand.

A Vector Checksum instruction. Elements from a second operand are added together one-by-one to obtain a first result. The adding includes performing one or more end around carry add operations. The first result is placed in an element of a first operand of the instruction. After each addition of an element, a carry out of a chosen position of the sum, if any, is added to a selected position in an element of the first operand.

A system includes an associative memory array and a concurrent adder. The memory array includes a plurality of sections, where each section includes cells arranged in rows and columns. The memory array stores bit j from a first multi-bit number and bit j from a second multi-bit number in a same column in section j. The concurrent adder performs, in parallel, multi-bit add operations of P pairs of multi-bit operands stored in columns of a memory array. Each pair of the P pairs is stored in a different column of the array and each add operation occurs in its associated different column.

A system includes an associative memory array and a concurrent adder. The memory array includes a plurality of sections, where each section includes cells arranged in rows and columns. The memory array stores bit j from a first multi-bit number and bit j from a second multi-bit number in a same column in section j. The concurrent adder performs, in parallel, multi-bit add operations of P pairs of multi-bit operands stored in columns of a memory array. Each pair of the P pairs is stored in a different column of the array and each add operation occurs in its associated different column.

Configurable circuits include an input selection region, a computation region, a switching region, and an output region. The input selection region includes a set of input multiplexers and selects and routes input signals. The computation region includes a set of lookup tables, each lookup table being coupled to selected signals from the input selection stage to generate a respective output signal. The switching region includes a set of output multiplexers, each output multiplexer being coupled to output signals from the set of lookup tables to provide circuit outputs responsive to respective output selection signals. The output region includes a domino logic stage, having a set of transistors, coupled to output signals from the set of lookup tables to provide circuit outputs that determine combinations of the signals output by the set of lookup tables.