Embodiments of the present disclosure pertain to multimodal digital multiplier circuits and methods. In one embodiment, partial product outputs of digital multiplication circuits are selectively inverted based on a mode control signal. The mode control signal may be set based on a format of the operands input to the multiplier. Example embodiments of the disclosure may multiply combinations of signed and unsigned input operands using different modes.

Multiplication circuitry comprises at least two adder arrays each to add a respective setof partial products to generate a respective product representing value representing a result of multiplication of a respective pair of portions of bits selected from first and second operands. The adder arrays comprise separate instances of hardware circuitry having at least two separate enable control signals for independently controlling whether at least two subsets of adder arrays are enabled or disabled. Booth encoding circuitry is shared between the adder arrays, to Booth encode the first operand to generate partial product selection indicators each corresponding to a Booth encoding of a respective Booth digit of the first operand. At least two adder arrays operate on respective partial products selected by partial product selection circuitry based on a same partial product selection indicator generated by the shared Booth encoding circuitry based on a same Booth digit of the first operand.

An apparatus, method and program are provided for calculating a result value to a required precision of a repeating iterative sum, wherein the repeating iterative sum comprises multiple iterations of an addition using an input value. Addition is performed in a single iteration of addition as a sum operation using overlapping portions of the input value and a shifted version of the input value, wherein the shifted version of the input value has a partial overlap with the input value. At least one result portion is produced by incrementing an input derived from the input value using the output from the sum operation and the result value is constructed using the at least one result portion to give the result value to the required precision. The repeating iterative sum is thereby flattened into a flattened calculation which requires only a single iteration of addition using the input value, thus facilitating the calculation of the result value of the repeating iterative sum.

A processing-in-memory (PIM) macro device and a method are disclosed. The PIM macro device includes a plurality of capacitor-based digital-to-analog converters (C-DACs) and a plurality of multiply-and-add (MAC) units. Each MAC unit includes a plurality of slices, where each slice comprises a plurality of clusters, and where each cluster includes a 6-transitor (6T) static random-access memory (SRAM) cell and a MAC module. Each MAC unit further includes a partial-sum combiner (P-Sum Combiner), an analog-to-digital converter (ADC), and a Share Line, a MAC Line, a plurality of wordlines (WLs), and a local bitline (LBL). The PIM macro device further includes an array of metal-oxide-metal (MOM) capacitors, where the MOM capacitors are shared between the C-DACs and the MAC units, an array of switches configured to be controlled to configure the MOM capacitors to perform a first operation and to reconfigure the MOM capacitors to perform a second operation.