In a low power hardware architecture for handling accumulation overflows in a convolver unit, an accumulator of the convolver unit computes a running total by successively summing dot products from a dot product computation module during an accumulation cycle. In response to the running total overflowing the maximum or minimum value of a data storage element, the accumulator transmits an overflow indicator to a controller and sets its output equal to a positive or negative overflow value. In turn, the controller disables the dot product computation module by clock gating, clamping one of its inputs to zero and/or holding its inputs to constant values. At the end of the accumulation cycle, the output of the accumulator is sampled. In response to a clear signal being asserted, the dot product computation module is enabled, and the running total is set to zero for the start of the next accumulation cycle.

In a novel computation device, a plurality of partial product generators is communicatively coupled to a binary number multiplier. The binary number is partitioned in the computation device into non-overlapping subsets of binary bits and each subset is coupled to one of the plurality of partial product generators. Each partial product generator, upon receiving, a subset of binary bits representing a number, generates a multiplication product of the number and a predetermined constant. The multiplication products from all partial product generators are summed to generate the final, product between the predetermined constant and the binary number. The partial product generators are constructed by logic gates and wires connected the logic gates including a AND gate. The partial product generators are free of memory elements.

The present disclosure relates to a multiplier, a multiply-accumulate circuit, and a convolution operation unit. The multiplier includes: one or more selection circuits, each of the one or more selection circuits respectively configured to select a target preset multiple of a first operand from a preset multiple of a first operand as a fourth operand according to a corresponding third operand, wherein the target preset multiple is equal to a value of the third operand; and a partial product summing circuit, each of one or more input terminals of the partial product summing circuit respectively connected to an output terminal of corresponding one of at least one or more selection circuits, wherein the partial product summing circuit is configured to calculate a partial product sum of one or more fourth operands from the one or more selection circuits.

According to an aspect of the disclosure, a computational processing method of multiplier, performed by a processor chip, includes: obtaining, based on n first operands a[k], a first operating part A including BIT(A) bits; obtaining x first encoded data Enc[m] by assigning a lowest bit of consecutive three-bit numbers spanning two adjacent first operands a[k] and a[k1] to 0, and performing Booth-encoding on the first operating part A; obtaining, based on n second operands b[k], n corresponding second operating parts B[k], each of which has BIT(B) bits; obtaining x partial products based on multiplying the x first encoded data Enc[m] with the n corresponding second operating parts; obtaining an accumulation result based on accumulating the x partial products; obtaining a multiplication result based on truncating the accumulation result; wherein, n, k, x, and m are integers, and wherein 0k<n, and 0m<x.

The present disclosure relates to a multiplier, a multiply-accumulate circuit, and a convolution operation unit. The multiplier includes: one or more selection circuits, each of the one or more selection circuits respectively configured to select a target preset multiple of a first operand from a preset multiple of a first operand as a fourth operand according to a corresponding third operand, wherein the target preset multiple is equal to a value of the third operand; and a partial product summing circuit, each of one or more input terminals of the partial product summing circuit respectively connected to an output terminal of corresponding one of at least one or more selection circuits, wherein the partial product summing circuit is configured to calculate a partial product sum of one or more fourth operands from the one or more selection circuits.