A redundant system for processing at least one signal is described wherein the redundant system has N+1 devices include N operational devices and one reserve device. The N operational devices and the reserve device are interconnected with each other. The redundant system includes a system control integrated within one of the devices of the redundant system. The redundant system further includes switches that are associated with the operational devices. In case of a failure of a respective operational device, the system control is configured to cause at least one of the devices to operate the switch associated with the respective operational device having the failure. Further, a method of operating a redundant system for processing at least one signal is described.

An application is provided as a compound virtual appliance having components to be hosted by virtual machines. Each component includes a set of virtual machine disks. Partial versions of the components are created by removing from each component each virtual machine disk determined to be a duplicate of a virtual machine disk of another component. A compact version of the compound virtual appliance is created by packing together the partial versions of the components and a single copy of each virtual machine disk having been determined to be a duplicate. The compact compound virtual appliance is deployed to a customer site. At the customer site, a complete version of the compound virtual appliance is reconstructed by adding back the single copy of each virtual machine disk having been determined to be a duplicate into each component having had the duplicate virtual machine disk removed.

A rendering optimisation identifies a draw call within a current render (which may be the first draw call in the render or a subsequent draw call in the render) and analyses a last shader in the series of shaders used by the draw call to determine whether the last shader samples from the one or more buffers at coordinates matching a current fragment location. If this determination is positive, the method further recompiles the last shader to replace an instruction that reads data from one of the one or more buffers at coordinates matching a current fragment location with an instruction that reads from the one or more buffers at coordinates stored in on-chip registers.

Multiple execution traces of an application are accessed. The multiple execution traces have been collected at a basic block level. Basic blocks in the multiple execution traces are scored. Scores for the basic blocks represent benefits of performing binary slimming at the corresponding basic blocks. Runtime binary slimming is performed of the application based on the scores of the basic blocks.

Information for use in a command script for a product dispensing system is compiled by sniffing packets associated with a print job that contains information associated with a product to be dispensed, filtering the packets so as to remove fields not associated with the print job, and combining the filtered packets to generate contiguous data associated with the print job. A command script for a product dispensing system is generated by receiving data associated with a print job that contains information associated with a product to be dispensed, extracting the information associated with the product from the print job data, organizing the information associated with the product into discrete informational units, and generating the command script based on the organized discrete information units.

Techniques for generating a dataflow graph include generating a first dataflow graph with a plurality of first nodes representing first computer operations in processing data, with at least one of the first computer operations being a declarative operation that specifies one or more characteristics of one or more results of processing of data, and transforming the first dataflow graph into a second dataflow graph for processing data in accordance with the first computer operations, the second dataflow graph including a plurality of second nodes representing second computer operations, with at least one of the second nodes representing one or more imperative operations that implement the logic specified by the declarative operation, where the one or more imperative operations are unrepresented by the first nodes in the first dataflow graph.

One or more execution traces of an application are accessed. The one or more execution traces have been collected at a basic block level. Basic blocks in the one or more execution traces are scored. Scores for the basic blocks represent benefits of performing binary slimming at the corresponding basic blocks. Runtime binary slimming is performed of the application based on the scores of the basic blocks.

Systems and methods for configuration management through information and code injection at compile time. An example method comprises: receiving a source code comprising one or more references to a variable; receiving metadata associated with the source code, wherein the metadata specifies a range of values of the variable; and identifying, in view of the range of values of the variable, a reachable section of the source code.

A processing system includes a compiler that automatically identifies sequences of instructions of tileable source code that can be replaced with tensor operations. The compiler generates enhanced code that replaces the identified sequences of instructions with tensor operations that invoke a special-purpose hardware accelerator. By automatically replacing instructions with tensor operations that invoke the special-purpose hardware accelerator, the compiler makes the performance improvements achievable through the special-purpose hardware accelerator available to programmers using high-level programming languages.

Various embodiments are generally directed to optimizing dataflow in automated transformation frameworks (e.g., compiler, runtime, etc.) for spatial architectures (e.g., Configurable Spatial Accelerator) that translate high-level user code into forms that use “streams” (e.g., Latency Insensitive Channels, line buffers) to reduce overhead, eliminate or improve the efficiency of redundant memory accesses, and improve overall throughput.