G06F8/4436

OPERATION EFFICIENCY MANAGEMENT WITH RESPECT TO APPLICATION RUN-TIME

Disclosed aspects relate to operation efficiency management in a shared pool of configurable computing resources. A first set of processing operations of a first application may be detected. A second set of processing operations of a second application may be detected. The first set of processing operations of the first application may be compared with the second set of processing operations of the second application. A substantial match of the first and second processing operations of the first and second applications may be determined. A single set of processing operations for both the first and second applications may be established.

Collaborative development of software programs based on service invocations

Assisting a user in developing a software program. A program code of the software program being under development is monitored to identify each code portion of the program code matching a matched one of a plurality of code patterns. A search request is submitted for searching, among a plurality of available services provided by corresponding service providers for the code patterns, each eligible service for the matched code pattern. An indication of at least one eligible service being found is received when a result of the search is positive, prompting the user to select a replacement service among the at least one eligible service in response to the positive result of the search. The code portion is replaced with an invocation of the replacement service on the corresponding service provider.

Module division assistance device, module division assistance method, and module division assistance program
10025558 · 2018-07-17 · ·

Provided are a module division assistance device, a module division assistance method, and a module division assistance program for automatically extracting a divisible module by utilizing information relating to a function used by a module. A keyword obtaining unit of an information processing device collects data relating to a function used by a module into keyword use data organized by modules, and a data analysis unit uses the data and a calculation method for an indivisibility calculation item specified by a user and stored in an indivisibility calculation item list, thereby calculating an indivisibility, and stores the indivisibility into indivisibility data. Then, with respect to a module to be subjected to division determination, a module division determination unit compares the indivisibility relating to a function relevant to the indivisibility calculation item specified by the user with a threshold value stored in the indivisibility calculation item list, thereby determining whether the module can be divided or not.

Symbol-matching between software versions
12141577 · 2024-11-12 · ·

Disclosed herein are techniques for matching symbols between code sets. Techniques include accessing a first symbol associated with a first version of software; accessing a second symbol associated with a second version of the software; comparing the first symbol to the second symbol; determining, based on the comparing, whether the second symbol is a functional equivalent of the first symbol; and performing a designation action based on whether the second symbol is a functional equivalent of the first symbol.

Method for compressing variable-length instructions including PC-relative instructions and processor for executing compressed instructions using an instruction table

A method for compressing instruction is provided, which includes the following steps. Analyze a program code to be executed by a processor to find one or more instruction groups in the program code according to a preset condition. Each of the instruction groups includes one or more instructions in sequential order. Sort the one or more instruction groups according to a cost function of each of the one or more instruction groups. Put the first X of the sorted one or more instruction groups into an instruction table. X is a value determined according to the cost function. Replace each of the one or more instruction groups in the program code that are put into the instruction table with a corresponding execution-on-instruction-table (EIT) instruction. The EIT instruction has a parameter referring to the corresponding instruction group in the instruction table.

Pre-compiler
09619215 · 2017-04-11 · ·

A method for reducing a compile time of a source program includes receiving, by a compiler hosted on a computer, the source program. The compiler may have a compile time that depends non-linearly on a size of a function in the source program. The method involves identifying a source function in the source program and splitting the source function in to two or more target functions having sizes smaller than a size of the source function. The method further includes compiling the source program with the two or more target functions having sizes smaller than a size of the source function replacing the source function in the source program.

SYSTEMS AND METHODS FOR SCALABLE HIERARCHICAL POLYHEDRAL COMPILATION

A system for compiling programs for execution thereof using a hierarchical processing system having two or more levels of memory hierarchy can perform memory-level-specific optimizations, without exceeding a specified maximum compilation time. To this end, the compiler system employs a polyhedral model and limits the dimensions of a polyhedral program representation that is processed by the compiler at each level using a focalization operator that temporarily reduces one or more dimensions of the polyhedral representation. Semantic correctness is provided via a defocalization operator that can restore all polyhedral dimensions that had been temporarily removed.

Method and apparatus for configuring a reduced instruction set computer processor architecture to execute a fully homomorphic encryption algorithm

Systems and methods for configuring a reduced instruction set computer processor architecture to execute fully homomorphic encryption (FHE) logic gates as a streaming topology. The method includes parsing sequential FHE logic gate code, transforming the FHE logic gate code into a set of code modules that each have in input and an output that is a function of the input and which do not pass control to other functions, creating a node wrapper around each code module, configuring at least one of the primary processing cores to implement the logic element equivalents of each element in a manner which operates in a streaming mode wherein data streams out of corresponding arithmetic logic units into the main memory and other ones of the plurality arithmetic logic units.

Systems and methods for code clustering analysis and transformation

The present application is directed towards systems and methods for cluster-based code analysis and transformation. Cluster-based analysis may group code objects based on their similarity across functional areas, such as where a code object is cloned in multiple areas (e.g. sort functions that are duplicated across areas, or reports or tables that are identical). In some implementations, objects may be grouped into clusters by type, or based on reading from or writing to a common table. In some implementations, clustering at different layers may be possible.

Method and Apparatus for Configuring a Reduced Instruction Set Computer Processor Architecture to Execute a Fully Homomorphic Encryption Algorithm

Systems and methods for configuring a reduced instruction set computer processor architecture to execute fully homomorphic encryption (FHE) logic gates as a streaming topology. The method includes parsing sequential FHE logic gate code, transforming the FHE logic gate code into a set of code modules that each have in input and an output that is a function of the input and which do not pass control to other functions, creating a node wrapper around each code module, configuring at least one of the primary processing cores to implement the logic element equivalents of each element in a manner which operates in a streaming mode wherein data streams out of corresponding arithmetic logic units into the main memory and other ones of the plurality arithmetic logic units.