Embodiments are provided for using metadata presence information to determine when to access a higher-level metadata table. It is determined that an incomplete hit occurred for a line of metadata in a lower-level structure of a processor, the lower-level structure being coupled to a higher-level structure in a hierarchy. It is determined that metadata presence information in a metadata presence table is a match to the line of metadata from the lower-level structure. Responsive to determining the match, it is determined to avoid accessing the higher-level structure of the processor.

Embodiments include a hierarchical metadata prediction system that includes a first line-based predictor having a first line for storage of metadata entries, and a second line-based predictor configured to store metadata entries from the first line-based predictor. The second line-based predictor has a second line, the second line including a plurality of containers, the plurality of containers including at least a first set of containers having a first size and a second set of containers having a second size. The system also includes a processing device configured to transfer one or more metadata entries between the first line-based predictor and the second-line based predictor. Embodiments also include a computer-implemented method and a computer program product.

Aspects of the invention include includes determining a first instruction in a processing pipeline, wherein the first instruction includes a compare instruction, determining a second instruction in the processing pipeline, wherein the second instruction includes a conditional branch instruction relying on the compare instruction, determining a predicted result of the compare instruction, and completing the conditional branch instruction using the predicted result prior to executing the compare instruction.

Each load/store queue entry holds a load/store physical address proxy (PAP) for use as a proxy for a load/store physical memory line address (PMLA). The load/store PAP comprises a set index and a way that uniquely identifies an L2 cache entry holding a memory line at the load/store PMLA when an L1 cache provides the load/store PAP during the load/store instruction execution. The microprocessor removes a line at a removal PMLA from an L2 entry, forms a removal PAP as a proxy for the removal PMLA that comprises a set index and a way, snoops the load/store queue with the removal PAP to determine whether the removal PAP is being used as a proxy for the removal PMLA, fills the removed entry with a line at a fill PMLA, and prevents the removal PAP from being used as a proxy for the removal PMLA and the fill PMLA concurrently.

A microprocessor prevents same address load-load ordering violations. Each load queue entry holds a load physical memory line address (PMLA) and an indication of whether a load instruction has completed execution. The microprocessor fills a line specified by a fill PMLA into a cache entry and snoops the load queue with the fill PMLA, either before the fill or in an atomic manner with the fill with respect to ability of the filled entry to be hit upon by any load instruction, to determine whether the fill PMLA matches load PMLAs in load queue entries associated with load instructions that have completed execution and there are other load instructions in the load queue that have not completed execution. The microprocessor, if the condition is true, flushes at least the other load instructions in the load queue that have not completed execution.

A data processing apparatus is provided. It includes control flow detection prediction circuitry that performs a presence prediction of whether a block of instructions contains a control flow instruction. A fetch queue stores, in association with prediction information, a queue of indications of the instructions and the prediction information comprises the presence prediction. An instruction cache stores fetched instructions that have been fetched according to the fetch queue. Post-fetch correction circuitry receives the fetched instructions prior to the fetched instructions being received by decode circuitry, the post-fetch correction circuitry includes analysis circuitry that causes the fetch queue to be at least partly flushed in dependence on a type of a given fetched instruction and the prediction information associated with the given fetched instruction.

In an embodiment, a processor may include an execution circuit to execute a plurality of instructions, a cache, and a decode circuit. The decode circuit may be to: detect a branch instruction in a program, the branch instruction to cause execution to follow either a first path or a second path in the program; and in response to a determination that the branch instruction is a hard to predict (HTP) branch, cause first and second sets of instructions to be stored in the cache, where the first set of instructions is included in the first path, and where the second set of instructions is included in the second path. Other embodiments are described and claimed.

In an embodiment, a processor may include an execution circuit to execute a plurality of instructions. The processor may also include a prediction circuit to: in response to a detection of a first target instruction in a program, identify a prediction data entry associated with a path history for the first target instruction, the identified prediction data entry to indicate an offset distance from the first target instruction to a predicted next taken branch of the program; and determine the predicted next taken branch of the program based on the offset distance indicated by the identified prediction data entry. Other embodiments are described and claimed.

Systems and methods are provided to monitor drift in branches of code associated with virtualized containers of cellular services developed in a virtual platform that include a set of core network components associated with a network slice to provide network functions and microservices wherein the virtual plane includes a development test environment for developing at least instructional sets of branch code; a development application to configure an instructional set including branch code for associating with one or more containers that clone a plurality of network functions and microservices of the cellular services deployed in physical infrastructure; and a drift monitoring tool that based on simulations from tests of a developed branch code executed with containers of cloned network functions and microservices provide data to developers of drift caused by the branch code to operations of the network functions and microservices contained in the physical infrastructure.

In one embodiment, a branch prediction control system is configured to move a mispredicted conditional branch from a smaller cache side that uses the lower complexity conditional branch predictor to one of the two large cache sides that uses the higher complexity conditional branch predictors. The move (write) is achieved according to a configurable probability or chance to escape misprediction recurrence and results in a reduced amount of mispredictions for the given branch instruction.