Aspects of the present disclosure relate to control of speculative demand loads. In some embodiments, the method includes receiving instructions for a branch in a program, detecting the branch load is in the cache, monitoring a number of completed loads for the program, determining a cache pollution ratio of executed loads to completed loads, providing the cache pollution ratio to a branch prediction unit, and altering load instructions for the branch based on the cache pollution ratio.

Limiting replay of load-based control independent (CI) instructions in speculative misprediction recovery in a processor. In misprediction recovery, load-based CI instructions are designated as load-based CI, data dependent (CIDD) instructions if a load-based CI instruction consumed forwarded-stored data of a store-based instruction. During the misprediction recovery, replayed load-based CIDD instructions will reevaluate an accurate source of memory load the correct data instead of consuming potentially faulty data that may have been forwarded by a store-based instruction that may have only existed in a mispredicted instruction control flow path. Limiting the replay of load-based CI instructions to only determined CIDD load-based instructions can reduce execution delay and power consumption in an instruction pipeline.

An integrated circuit comprising instruction processing circuitry for processing a plurality of program instructions and instruction prediction circuitry. The instruction prediction circuitry comprises circuitry for detecting successive occurrences of a same program loop sequence of program instructions. The instruction prediction circuitry also comprises circuitry for predicting a number of iterations of the same program loop sequence of program instructions, in response to detecting, by the circuitry for detecting, that a second occurrence of the same program loop sequence of program instructions comprises a same number of iterations as a first occurrence of the same program loop sequence of program instructions.

A branch predictor is provided with a branch state buffer, branch prediction save circuitry responsive to a branch prediction save event associated with a given execution context to save at least a portion of the active branch prediction state associated with the given execution context to a branch state buffer; and branch prediction restore circuitry responsive to a branch prediction restore event associated with the given execution context to restore active branch prediction state based on previously saved branch prediction state stored in the branch state buffer for the given execution context. This is useful for reducing the performance impact of mitigating against speculative side-channel attacks.

An apparatus and method are provided for making predictions for instruction flow changing instructions. The apparatus has a fetch queue that identifies a sequence of instructions to be fetched for execution by execution circuitry, and prediction circuitry for making predictions in respect of instruction flow changing instructions, and for controlling which instructions are identified in the fetch queue in dependence on the predictions. The prediction circuitry has a target prediction storage used to identify target addresses for instruction flow changing instructions that are predicted as taken. The target prediction storage comprises at least one entry that is configurable as a multi-taken entry to indicate that a source instruction flow changing instruction identified by that entry is a first instruction flow changing instruction with an associated first target address that identifies a series of instructions that is expected to exhibit static behaviour and that terminates with a second instruction flow changing instruction, where the second instruction flow changing instruction is unconditionally taken and has an associated second target address. The prediction circuitry is arranged, when making a prediction for a chosen instruction flow changing instruction that is identified by a multi-taken entry in the target prediction storage, to identify with reference to target address information stored in that multi-taken entry both the series of instructions and a target instruction at the second target address. It then causes the series of instructions and the target instruction to be identified in the fetch queue, and begins making further predictions starting from the target instruction at the second target address.

Aspects of the present disclosure relate to control of speculative demand loads. In some embodiments, the method includes receiving instructions for a branch in a program, detecting the branch load is in the cache, monitoring a number of completed loads for the program, determining a cache pollution ratio of executed loads to completed loads, providing the cache pollution ratio to a branch prediction unit, and altering load instructions for the branch based on the cache pollution ratio.

An apparatus comprises processing circuitry to perform data processing in response to instructions fetched from an instruction cache, an instruction prefetcher to speculatively prefetch instructions into the instruction cache, and a branch predictor having at least one branch prediction structure to store branch prediction data for predicting at least one branch property of an instruction fetched for processing by the processing circuitry. On prefetching of a given instruction into the instruction cache by the instruction prefetcher, the branch predictor is configured to perform a prefetch-triggered update of the branch prediction data based on information derived from the given instruction prefetched by the instruction prefetcher. This can help to improve performance, especially for workloads with a high branch density and large branch re-reference interval.

A processing device includes a branch IP table and branch predication circuitry coupled to the branch IP table. The branch predication circuitry to: determine a dynamic convergence point in a conditional branch of set of instructions; store the dynamic convergence point in the branch IP table; fetch a first and second speculative path of the conditional branch; while determining which of the first speculative path and the second speculative path is a taken path of the conditional branch and determining whether a dynamic convergence point is fetched corresponding to the stored dynamic convergence point, stall scheduling of instructions of the first speculative path and the second speculative path; and in response to determining that one of the first speculative path and the second speculative path is the taken path and the fetched dynamic convergence point corresponds to the stored convergence point, resume scheduling of the instructions of the taken path.

A computer system includes a branch detection module and a branch predictor module. The branch detection module determines that a first program branch is a possible call branch having a next sequential instruction address (NSIA), and determines that a first routine branch is a possible return capable branch having the first routine instruction address that is a detected as being offset. The branch predictor module determines that a second program branch is a possible call branch having a next sequential instruction address (NSIA), and determines that a second routine branch is a predicted return branch having a predicted target instruction address based on the NSIA of the second program branch and the predicted offset.

An apparatus comprises processing circuitry to perform data processing in response to instructions; and a branch predictor to predict a branch outcome for a given branch instruction as one of taken and not-taken, based on branch prediction state information indexed based on at least one property of the given branch instruction. In a static branch prediction mode of operation, the branch predictor predicts the branch outcome based on static values of the branch prediction state information set independent of actual branch outcomes of branch instructions which are executed by the processing circuitry while in the static branch prediction mode. The static values of the branch prediction state information are programmable.