A data processing apparatus is provided, which is able to provide predictions for hard to predict instructions. Prediction circuitry generates predictions relating to predictable instructions in a stream, where the prediction circuitry comprises storage circuitry to store, in respect of each of the predictable instructions, a reference to a set of monitored instructions in the stream to be used for generating predictions for the predictable instructions. Processing circuitry receives the predictions from the prediction circuitry and executes the predictable instructions in the stream using the predictions. Programmable instruction correlation parameter storage circuitry stores a given correlation parameter between a given predictable instruction in the stream and a subset of the set of monitored instructions of the given predictable instruction, to assist the prediction circuitry in generating the predictions. If the programmable instruction correlation parameter storage circuitry is currently storing the given correlation parameter, the prediction circuitry generates a given prediction relating to the given predictable instruction based on the subset of the set of monitored instructions indicated in the programmable instruction correlation parameter storage circuitry. Otherwise the prediction circuitry generates the given prediction relating to the given predictable instruction based on the set of monitored instructions indicated in the storage circuitry.

An electronic device includes a processor, a branch predictor in the processor, and a predictor controller in the processor. The branch predictor includes multiple prediction functional blocks, each prediction functional block configured for generating predictions for control transfer instructions (CTIs) in program code based on respective prediction information, the branch predictor configured to select, from among predictions generated by the prediction functional blocks for each CTI, a selected prediction to be used for that CTI. The predictor controller keeps a record of prediction functional blocks from which the branch predictor previously selected predictions for CTIs. The predictor controller uses information from the record for controlling which prediction functional blocks are used by the branch predictor for generating predictions for CTIs.

Techniques are disclosed for address manipulation using indices and tags. A first index is generated from bits of a processor program counter, where the first index is used to access a branch predictor bimodal table. A first branch prediction is provided from the bimodal table, based on the first index. The first branch prediction is matched against N tables, where the tables contain prior branch histories, and where: the branch history in table T(N) is of greater length than the branch history of table T(N-1), and the branch history in table T(N-1) is of greater length than the branch history of table T(N-2). A processor address is manipulated using a greatest length of hits of branch prediction matches from the N tables, based on one or more hits occurring. The branch predictor address is manipulated using the first branch prediction from the bimodal table, based on zero hits occurring.

A microprocessor with a solution to instruction fetching failure is shown. The branch predictor and the instruction cache are decoupled by a fetch target queue. In response to instruction fetching failure of a target fetching address, the instruction cache regains the target fetching address from the fetch target queue to restart the failed instruction fetching.

Systems and methods are disclosed for secure control flow prediction. Some implementations may be used to eliminate or mitigate the Spectre-class of attacks in a processor. For example, an integrated circuit (e.g., a processor) for executing instructions includes a control flow predictor with entries that include respective indications of whether the entry has been activated for use in a current process, wherein the integrated circuit is configured to access the indication in one of the entries that is associated with a control flow instruction that is scheduled for execution; determine, based on the indication, whether the entry of the control flow predictor associated with the control flow instruction is activated for use in a current process; and responsive to a determination that the entry is not activated for use in the current process, apply a constraint on speculative execution based on control flow prediction for the control flow instruction.

In one embodiment, a microprocessor, comprising: a branch prediction table comprising plural entries, wherein at least a portion of the plural entries corresponds to an indirect branch type; and an indirect valid table; wherein based on an indirect branch instruction fetch, an entry corresponding to an indirect branch instruction in the branch prediction table is configured as invalid based on clearing a corresponding entry in the indirect valid table.

In one embodiment, a method implemented in a microprocessor, the method comprising: receiving a fetched branch instruction; performing a privilege level test on a fetched branch instruction using a privilege level indicated by a first tag corresponding to a privilege level in a branch prediction table comprising plural entries, each of the plural entries comprising a tag corresponding to a privilege level; and providing a prediction branch miss for the fetched branch instruction based on a failure of the privilege level test.

An apparatus has processing circuitry, and history storage circuitry to store local history records. Each local history record corresponds to a respective subset of instruction addresses and tracks a sequence of observed instruction behaviour observed for successive instances of instructions having addresses in that subset. Pointer storage circuitry to store a shared pointer shared between the local history records. The shared pointer indicates a common storage position reached in each local history record. Prediction circuitry determines predicted instruction behaviour for a given instruction address based on a selected portion of a selected local history record stored in the history storage circuitry. The prediction circuitry selects the selected local history record based on the given instruction address and selects the selected portion based on the shared pointer.

In one embodiment, a branch prediction control system is configured to move a mispredicted conditional branch from a smaller cache side that uses the lower complexity conditional branch predictor to one of the two large cache sides that uses the higher complexity conditional branch predictors. The move (write) is achieved according to a configurable probability or chance to escape misprediction recurrence and results in a reduced amount of mispredictions for the given branch instruction.

A processor core executes a first process. The first process is associated with a first context tag that is generated based on context information controlled by an operating system or hypervisor of the processing system. A branch prediction structure selectively provides the processor core with access to an entry in the branch prediction structure based on the first context tag and a second context tag associated with the entry. The branch prediction structure selectively provides the processor core with access to the entry in response to the first process executing a branch instruction. Tagging entries in the branch prediction structure reduces, or eliminates, aliasing between information used to predict branches taken by different processes at a branch instruction.