A fog service layer architecture is disclosed using hierarchical fog node deployment including the co-existence and interactions of the fog node with a cloud node. The architecture also includes a list of functions, capabilities or services that are hosted in each fog node. One or more fog management procedures may be run between fog nodes (or between fogs and the cloud) and may comprise a fog capability discovery procedure, a fog connection verification procedure, and a fog capability status report procedure. In addition, fog nodes may be configured to interact with each other to get particular services using one or more fog service procedures described herein.

Technologies for providing hardware resources as a service with direct resource addressability are disclosed. According to one embodiment of the present disclosure, a device receives a request to access a destination accelerator device in an edge network, the request specifying a destination address assigned to the destination accelerator device. The device determines, as a function of the destination address, a location of the destination accelerator device and sends the request to the destination accelerator device.

Various embodiments are generally directed to techniques for supporting the distributed execution of a task routine among multiple secure controllers incorporated into multiple computing devices. An apparatus includes a first processor component and first secure controller of a first computing device, where the first secure controller includes: a selection component to select the first secure controller or a second secure controller of a second computing device to compile a task routine based on a comparison of required resources to compile the task routine and available resources of the first secure controller; and a compiling component to compile the task routine into a first version of compiled routine for execution within the first secure controller by the first processor component and a second version for execution within the second secure controller by a second processor component in response to selection of the first secure controller. Other embodiments are described and claimed.

An information handling system may include at least one central processing unit (CPU); and a plurality of special-purpose processing units. The information handling system may be configured to: receive information regarding cooling characteristics of the plurality of special-purpose processing units; and assign identification (ID) numbers to each of the plurality of special-purpose processing units in an order that is determined based at least in part on the cooling characteristics.

The current document is directed to methods and systems that automatically deploy and manage applications that are associated with hardware dependencies. As one example, many machine-learning-based applications use specialized hardware accelerators during training phases since, in many cases, training of machine-learning-based applications and systems would be computationally intractable without the increased computational bandwidth provided by hardware accelerators. However, such hardware dependencies may prevent machine-learning-based applications from being deployed and managed effectively by widely used automated orchestration systems, and manual deployment of applications with hardware dependencies may suffer significant inefficiencies and problems related to maintenance downtime within distributed computer systems. The currently disclosed methods and systems provide centralized maintenance-and-hardware-dependency scheduling information along with an asynchronous protocol for access to the maintenance-and-hardware-dependency scheduling information by automated orchestration systems and managers and administrators of distributed computer systems to facilitate efficient deployment of machine-learning-based applications with hardware dependencies.

In one implementation, a method of sharing a physical device between multiple virtual machines is provided. The method includes receiving, from a first virtual machine, a request to access a physical device of a computing device. The method also includes assigning, by a processing device, the physical device to the first virtual machine in view of power state information associated with the physical device of the computing device, wherein the power state information is received from one or more other virtual machines of the computing device.

In some embodiments a distributed computing system is provided that includes a plurality of different feature modules and a matching engine. The different feature modules each provide different processing for handling parent requests and submitting, to the matching engine, commands for child data transaction requests that are associated with the parent request.

Disclosed are various embodiments for optimized memory tiering. An ideal tier size for a first memory and an ideal tier size for a second memory can be determined for a process. Then, a host computing device can be identified that can accommodate the ideal tier size for the first memory and the second memory. Subsequently, the process can be assigned to the host computing device.

In some embodiments a distributed computing system is provided that includes a plurality of different feature modules and a matching engine. The different feature modules each provide different processing for handling parent requests and submitting, to the matching engine, commands for child data transaction requests that are associated with the parent request.

A method, product and apparatus comprising: obtaining an indication of an execution task to be performed by a quantum computer, wherein the execution task comprises executing, by the quantum computer, a quantum program for a number of times that is larger than two times: obtaining a graph comprising nodes that are connected by edges, the graph represents a gate-level implementation of the quantum program, the graph depicts quantum restrictions of the quantum program; and packing multiple graphs according to the quantum restrictions to synthesize a joint circuit, the joint circuit is configured, when executed by the quantum computer, to implement the execution task, the multiple graphs comprise at least one instance of the graph, the one instance of the graph represents a single execution of the quantum program, whereby execution of the joint circuit implements execution of the quantum program for the number of times.