A memory device includes a memory component that stores data and a processor. The processor may receive requests from a requesting component to perform a plurality of data operations, generate a plurality of packets associated with the plurality of data operations, and continuously transmit each of the plurality of packets until each of the plurality of packets are transmitted. Each of the plurality of packets after the first packet of the plurality of packets is transmitted on a subsequent clock cycle immediately after a previous packet is transmitted.

A semiconductor memory device including: a buffer die; memory dies stacked on the buffer die; and TSVs, at least one of the memory dies includes: a memory cell array; an error correction code (ECC) engine; an error information register; and a control logic circuit configured to control the ECC engine to perform a read-modify-write operation, wherein the control logic circuit is configured to: record, in the error information register, a first address associated with a first codeword based on the an generation signal and a first syndrome obtained by an ECC decoding; and determine an error attribute of the first codeword based on a change of the first syndrome, recorded in the error information register, based on a plurality of read-modify-write operations.

A method of operating a system running a virtual machine that executes an application and an operating system (OS) includes performing first address translation from first virtual addresses to first physical addresses, identifying faulty physical addresses among the first physical addresses, each faulty physical address corresponding to a corresponding first physical address associated with a faulty memory cell, analyzing a row address and a column address of each faulty physical address and specifying a fault type of the faulty physical addresses based on the analyzing of the row address and the column address of each faulty physical address, and performing second address translation from second virtual addresses to second physical addresses based on a faulty address, thereby excluding the faulty address from the second physical addresses.

Systems, apparatuses, and methods related to modified parity data using a poison data unit. An example method can include receiving, from a controller of a memory device, a first set of bits including data and a second set of at least one bit indicating whether the first set of bits comprises one or more erroneous or corrupted bits. The method can further include generating, at an encoder of the memory device, parity data associated with the first set of bits. The method can further include generating, at logic of the memory device, modified parity data with the parity data component and the second set of at least one bit. The method can further include writing the first set of bits and the modified parity data in an array of the memory device.

Memory controllers, devices and associated methods are disclosed. In one embodiment, a memory controller includes write circuitry to transmit write data to a memory device, the write circuitry includes a write error detection correction (EDC) encoder to generate first error information associated with the write data. Data bus inversion (DBI) circuitry conditionally inverts data bits associated with each of the write data words based on threshold criteria. Read circuitry receives read data from the memory device. The read circuitry includes a read EDC encoder to generate second error information associated with the received read data. Logic evaluates the first and second error information and conditionally reverse-inverts at least a portion of the read data based on the decoding.

It is aimed to detect an error of an address abnormality in a memory. An address error detection information generating unit generates address error detection information for detecting an error relating to an access address for a memory. A control part stores the address error detection information generated by the address error detection information generating unit in the memory at a time of write access. An error detecting part compares the address error detection information generated by the address error detection information generating unit with the address error detection information stored in the memory to detect an error at a time of read access.

A non-volatile dual in-line memory module (NVDIMM) instantiates first and second partitions of non-volatile memory. The first partition is reserved and is not accessible to an operating system instantiated. The second partition is accessible to the operating system. A processor detects a first bad memory location in the second partition, stores a first system physical address of the first bad memory location to a system bad memory locations list, and stores a first DIMM physical address of the first bad memory location to a first NVDIMM bad memory locations list in the first partition.

An information handling system may include a central processing unit (CPU), a graphics processing unit (GPU) including a plurality of processing cores, a memory coupled to the CPU and to the GPU, and a basic input/output system (BIOS). While the information handling system is in a pre-boot environment and prior to initialization of an operating system of the information handling system, the BIOS may cause the central processing unit to select respective portions of the memory for failure testing; and cause individual ones of the plurality of processing cores of the GPU to carry out the failure testing of the respective portions of the memory.

A solid state disk access method includes: determining, in response to a read error, a first read voltage of the current data block according to a current data storage time interval to which a data storage time of the current data block belongs; performing reread error correction on the data in the current data block based on the first read voltage; determining, if reread error correction of the current data block fails, a second read voltage corresponding to the current data block according to the current data storage time interval and a preset data read rule that is determined based on the data storage time interval and the number of data reads; and performing reread error correction on the data in the current data block based on the second read voltage until the reread error correction of the current data block meets a preset reread error correction condition.

A semiconductor device includes a master circuit which outputs a first write request signal for requesting to write data, a bus which receives the data and the first write request signal, a bus control unit which is arranged on the bus, generates an error detection code for the data and generates a second write request signal which includes second address information corresponding to first address information included in the first write request signal and memory controllers which each write the data into a storage area of an address designated by the first write request signal and writes the error detection code into a storage area of an address designated by the second write request signal in the storage areas of memories.