A flash memory system may include a flash memory and a circuit for performing operations of the flash memory. The circuit may be configured to estimate slope information of a plurality of threshold voltage samples based on a first read operation on the flash memory with a first reference voltage. The circuit may be configured to generate soft information based on the estimated slope information. The circuit may be configured to decode a result of a second read operation on the flash memory based on the soft information.

Embodiments of the present disclosure provide a method, device, and computer program product for error evaluation. A method for error evaluation comprises in accordance with a determination that an error occurs in a data protection system, obtaining context information related to an operation of the data protection system; determining, based on the context information and using a trained deep learning model, a type of the error in the data protection system from a plurality of predetermined types, the deep learning model being trained based on training context information and a label on a ground-truth type of an error associated with the training context information; and providing the determined type of the error in the data protection system. In this way, it is possible to achieve automatic classification of errors in the data protection system, thereby improving the efficiency in error classification and saving the operation costs. Therefore, more rapid and more accurate measures can be taken to handle the errors.

An information handling system includes a processor and an embedded controller. The processor executes operations while the information handling system is in an active power state. The embedded controller communicates with the processor. While the information handling system is in the active power state, the embedded controller detects a trigger event. In response to the trigger event, the embedded controller provides a ping command to the processor. Based on a response to the ping command not being received, the embedded controller determines a processor freeze, stores forensic data associated with the processor freeze, and stores an indication to perform a processor freeze recovery during a next boot operation.

Methods, systems, and apparatus for detecting single event effects. The system includes a first-modulus digital logic unit and a second-modulus digital logic unit each configured to reduce one or more operands by a respective modulus, apply an arithmetic compute logic to the reduced operands to produce a respective compute output, and reduce the respective compute output by their respective modulus. The system includes a kernel digital logic unit configured to apply the arithmetic compute logic to the operands to produce a kernel compute output, output the kernel compute output reduced by the first modulus, and output the kernel compute output reduced by the second modulus. The system includes a detector configured to detect a single event effect based on the reduced first compute output, the kernel compute output reduced by the first modulus, the reduced second compute output, and the kernel compute output reduced by the second modulus.

A memory module includes a first channel of first data memories and a first error correction code (ECC) memory, and a second channel of second data memories and a second ECC memory. Each first data memory transmits a corresponding first data set of first data sets with a memory controller. Each first data set corresponds to a burst length. Each second data memory transmits a corresponding second data set of the second data sets with the memory controller. Each second data set corresponds to the burst length. The first ECC memory stores first sub parity data for detecting at least one error in all of the first data sets stored in the first data memories. The second ECC memory stores second sub parity data for detecting at least one error in all of the second data sets stored in the second data memories.

A memory module includes a first channel of first data memories and a first error correction code (ECC) memory, and a second channel of second data memories and a second ECC memory. Each first data memory transmits a corresponding first data set of first data sets with a memory controller. Each first data set corresponds to a burst length. Each second data memory transmits a corresponding second data set of the second data sets with the memory controller. Each second data set corresponds to the burst length. The first ECC memory stores first sub parity data for detecting at least one error in all of the first data sets stored in the first data memories. The second ECC memory stores second sub parity data for detecting at least one error in all of the second data sets stored in the second data memories.

A solid state comprising: memory cells programmable with threshold voltages, each one associated with a respective bit pattern and variable over the memory cells thereby defining a respective threshold voltage distribution. Each pair of adjacent bit patterns can be discriminated by a respective first reference voltage between the threshold voltages associated with the pair of adjacent bit patterns, and a controller for storing LLR tables; for each bit pattern combination comprising first, second and third bit patterns respectively associated with the first reference voltage, a second reference voltage higher than the first reference voltage, and a third reference voltage lower than the first reference voltage, each LLR table has an error information when that bit pattern combination is associated with respective threshold voltages that, based on the threshold voltage distributions, are inconsistent with each other, or a LLR value otherwise.

A memory system includes a nonvolatile memory including memory cells, and a memory controller. The memory controller is configured to read first data through application of a first read voltage to each of the memory cells, perform a first decoding process with respect to the first data, when the first decoding process fails, perform a tracking process. The tracking process includes reading second data indicating a threshold voltage level of each of the memory cells through application of a plurality of second read voltages to each of the memory cells, and obtaining, with respect to each of the memory cells, likelihood information using the second data. The second read voltages are shifted by a predetermined amount. The memory controller is further configured to perform a second decoding process with respect to the second data using the likelihood information.

Methods, systems, and apparatuses to improve the handling of exceptions during the retrieval and processing of health records from various data sources are provided. During the retrieval and processing of health records, exceptions to typical behavior are recorded with context at the data extraction protocol level, at the health record level and at the level of elements with the document. Accordingly, insights may be developed and configurations, rules, or coding changes, based on the detected exceptions may be proposed. In some instances, an operator may be notified about the exceptions such that the operator may act on the insight. In some instances, the processing of extracted records (documents, messages) may be deferred until the operator has made appropriate changes to configuration, rules, or code. In some instances, the system may supplement and/or replace the operator with machine learning engines that act on the developed insights.

A solid state drive is proposed. The solid state drive comprises a plurality of memory cells each one programmable with a threshold voltage among a plurality of threshold voltages; each threshold voltage is associated with a respective bit pattern among a plurality of bit patterns and is variable over the plurality of memory cells thereby defining a respective threshold voltage distribution. Each pair of adjacent bit patterns can be discriminated, during a read operation, by a respective first reference voltage between the threshold voltages associated with the pair of adjacent bit patterns. The solid state drive also comprises a controller for storing a plurality of LLR tables; for each bit pattern combination comprising first, second and third bit patterns respectively associated with the first reference voltage, a second reference voltage higher than the first reference voltage, and a third reference voltage lower than the first reference voltage, each LLR table has an error information when that bit pattern combination is associated with respective threshold voltages that, based on the threshold voltage distributions, are inconsistent with each other, or a LLR value indicative of an outcome bit pattern and of an indication of reliability of the outcome bit pattern otherwise.