An error correction circuit includes a memory that stores at least one decoding parameter, a low density parity check (LDPC) decoder that includes a first variable node storing one bit of the data, receives the at least one decoding parameter from the memory, decides a degree of the first variable node based on the at least one decoding parameter, and decides a decoding rule necessary for decoding of the one bit based on the degree of the first variable node, and an adaptive decoding controller that outputs corrected data based on a decoding result of the LDPC decoder.

Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. One or more error correction code (ECC) may be used to determine if the bits of information contain any errors. To mitigate the effects of failures of adjacent memory cells, the information may be divided into a first group and a second group, where each group contains information from memory cells which are non-adjacent to other memory cells of that group. Each group of information may include data bits and parity bits used to correct those data bits. For example, as part of a read operation, a first ECC circuit may receive information from even numbered memory cells, while a second ECC circuit may receive information from odd numbered memory cells.

Provided is a communication device, including: a transmission and reception unit that transmits and receives a signal with an other communication device; an error detection unit that detects an occurrence of an error by having the transmission and reception unit receive a preamble specifying a type of data to be transmitted next, and comparing a bit sequence of a signal received following the preamble to a bit sequence that should be transmitted for the type specified for transmission by the preamble; and a conflict avoidance unit that, if the occurrence of an error is detected by the error detection unit, instructs the transmission and reception unit to transmit a clock corresponding to a certain number of bits following the preamble, and then transmit an abort signal giving an instruction to terminate communication partway through.

A memory system includes a non-volatile memory and a controller. The controller is configured to perform iterative correction on a plurality of frames of data read from the non-volatile memory. The iterative correction includes performing a first error correction on each of the frames including a first frame having errors not correctable by the first error correction, generating a syndrome on a set of second frames that include the first frame, performing a second error correction on the second frames using the syndrome, and performing a third error correction on the first frame. Each of the frames includes user data and first parity data used in the first error correction, the first parity data of the first frame also being used in the third error correction.

A memory system includes a non-volatile memory and a controller. The controller is configured to perform iterative correction on a plurality of frames of data read from the non-volatile memory. The iterative correction includes performing a first error correction on each of the frames including a first frame having errors not correctable by the first error correction, generating a syndrome on a set of second frames that include the first frame, performing a second error correction on the second frames using the syndrome, and performing a third error correction on the first frame. Each of the frames includes user data and first parity data used in the first error correction, the first parity data of the first frame also being used in the third error correction.

Disclosed is a memory device including an error logic unit suitable for determining whether an error is present in command signals to generate a command error signal; a replica delay circuit suitable for replicating a delay value of the error logic unit and generating an input strobe signal by delaying a strobe signal of the command signals; an output strobe signal generation circuit suitable for generating an output strobe signal activated after a command error latency elapses from a time point at which the command signals are received; and a pipe circuit suitable for receiving and storing the command error signal in response to the input strobe signal and outputting the stored command error signal in response to the output strobe signal.

A memory system comprises a memory device including plural memory blocks, and a controller coupled to the memory device. The controller controls the memory device to read a first group including plural data items and a parity associated with the plural data items from first locations in the plural memory blocks. The controller generates a new parity when the plural data items and the parity include plural errors, substitute one of the plural errors with the new parity and another of the plural errors with dummy data. The controller controls the memory device to program a second group including the new parity and the dummy data in second locations in the plural memory blocks. The second locations are different from the first locations.

A memory controller generates error codes associates with write data and a write address and provides the error codes over a dedicated error detection code link to a memory device during a write operation. The memory device performs error detection, and in some cases correction, on the received write data and write address based on the error codes. If no uncorrectable errors are detected, the memory device furthermore stores the error codes in association with the write data. On a read operation, the memory device outputs the error codes over the error detection code link to the memory controller together with the read data. The memory controller performs error detection, and in some cases correction, on the received read data based on the error codes.

A RAM chip includes host dies and parity dies. A memory controller receives system data to be stored on the RAM chip that is in excess of the storage capacity of the host dies. The memory controller encodes the system data in the parity symbols of the parity dies. The system data is retrieved by decoding the parity symbols and identifying the system data from the decoded information.

A first serializing stage is provided with a stream of data words composed of sub-words that each have values that associate each of the sub-words with the same error detection code value. For example, the values selected for each sub-word may each be associated with even parity. One or more serializing stages time-multiplex the sub-words into a stream of sub-word sized data. At the serializing stage that receives sub-word sized data stream, the data is checked to determine whether any of the sub-words is no longer associated with the error detection code value. Serializing/deserializing stages are selectively controlled to replace one or more data bits from a word being serialized/deserialized with an error detecting code value (e.g., parity). A subsequent serializing/deserializing stage is enabled to use the inserted error detecting code values and the data in the received words to determine whether an error has occurred.