Patent classifications
G06F11/1423
Resolving erred 10 flows
A method for resolving an erred input/output (IO) flow, the method may include (i) sending over a path a remote direct write request associated with a certain address range; wherein the path is formed between a compute node of a storage system to a storage drive of the storage system; (ii) receiving by the compute node an error message related to the remote direct write request; wherein the error message does not indicate whether an execution of the remote direct write request failed or is only temporarily delayed; (iii) responding by the compute node to the error message by (a) preventing from sending one or more IO requests through the path, (b) preventing from sending at least one IO requests aimed to the certain address range; and (c) requesting, using a management communication link, to force an execution of pending IO requests that are related to the path; and (iv) reuse the path, by the compute node, following an indication that there are no pending IO requests that are related to the path.
Selective endpoint isolation for self-healing in a cache and memory coherent system
A cache and memory coherent system includes multiple processing chips each hosting a different subset of a shared memory space and one or more routing tables defining access routes between logical addresses of the shared memory space and endpoints that each correspond to a select one of the multiple processing chips. The system further includes a coherent mesh fabric that physically couples together each pair of the multiple processing chips, the coherent mesh fabric being configured to execute routing logic for updating the one or more routing tables responsive to identification of a first processing chip of the multiple processing chips hosting a defective hardware component, the update to the routing tables being effective to remove all access routes having endpoints corresponding to the first processing chip.
METHOD OF RECOVERING BOOTLOADER IN MOBILE ELECTRONIC DEVICE AND BOOTLOADER RECOVERY SYSTEM PERFORMING THEREOF
In a method of recovering a bootloader in a mobile electronic device, a bootloader recovery signal is transmitted from a bridge board to the mobile electronic device. The bridge board includes a first internal path and a second internal path. The mobile electronic device includes a third internal path and a fourth internal path. The bootloader recovery request signal is transmitted based on the first internal path and the third internal path. a boot mode of the mobile electronic device is changed based on the first internal path and the fourth internal path in response to receiving the bootloader recovery request signal. Bootloader recovery data is transmitted from a host device to the bridge board based on the changed boot mode. The bootloader recovery data is transmitted from the bridge board to the mobile electronic device based on the second internal path and the third internal path.
SYSTEM AND METHOD OF ANALYZING UPDATE READINESS FOR DISTRIBUTED SOFTWARE SYSTEMS
The disclosure provides for analyzing upgrade and migration readiness. Embodiments include receiving an indication to upgrade a software product and a selected upgrade path identifying a target-upgrade version. Embodiments include accessing an array of pre-upgrade procedures comprising code for identifying one or more conditions that must be met before the software product can be upgraded based on the accessed array being associated with the software product. Embodiments include executing one or more of the pre-upgrade procedures in advance of upgrading the software product. Embodiments include accessing one or more autonomous remediation scripts from the repository based on identification of one or more failed pre-upgrade procedures. Embodiments include executing the one or more autonomous remediation scripts to cure the one or more failed pre-upgrade procedures and initiating an upgrade of the software product based on identifying that the array of pre-upgrade procedures successfully completed execution.
FLEXIBLE HIGH-AVAILABILITY COMPUTING WITH PARALLEL CONFIGURABLE FABRICS
Composable computing architectures with an interconnection fabric to provide high availability and fault tolerance are described. An interconnection fabric routes packets between compute resources, memory resources, and input/output (I/O) resources. A fabric manager is coupled with the interconnection fabric to receive an I/O or memory requirement for a compute workload for a host device, and to map individual I/O or memory resources from the plurality of I/O resources to individual compute resources from the plurality of compute resource and to dynamically map individual I/O resources from the plurality of I/O resources based on received resource requests.
ARTIFICIAL NEURAL NETWORK REMAPPING IN MEMORY
An artificial neural network can be allocated to memory and operated. An error can occur in the memory and/or be detected in the memory. Layers of the artificial neural network can be remapped in the memory at least partially in response to the error. Performance of the artificial neural network can be evaluated before and/or after the remapping.
Techniques for performing backups using hints
Processing I/O operations may include: receiving, at a data storage system, an I/O operation from a host, wherein the I/O operation is directed to a logical address and includes an I/O tag used in connection with performing data reduction processing for first data stored at the logical address; and performing processing to back up a data set including the first data stored at the logical address. The processing may include: sending, from the data storage system to a backup application, the data set and hints regarding the first data set, wherein the hints include a first hint determined in accordance with the I/O tag from the host; performing, in accordance with the hints, data reduction processing of the data set to generate a second data set; and storing the second data set on one or more backup storage devices.
Redundant controllers or input-output gateways without dedicated hardware
A method of fault-tolerant process control includes providing a network process control system in an industrial processing facility (IPF) including a plant-wide network coupling a server to computing platforms each including computing hardware and memory hosting a software application for simultaneously supporting a process controller and another process controller or an I/O gateway. The computing platforms are coupled together by a private path redundancy network for providing a hardware resource pool. At least some of the computing platforms are directly coupled by an I/O mesh network to a plurality of I/O devices to field devices that are coupled to processing equipment. Upon detecting at least one failing device in the hardware resource pool, over the private path redundancy network a backup is placed into service for the failing device from the another process controller or I/O gateway that is at another of the computing platforms in the hardware resource pool.
System, method, and computer program for managing fault recovery in network function virtualization (NFV) based networks
According to one aspect of the present invention there is provided a system, method, and computer program product for recovering from a network failure in a communication network using network function virtualization (NFV-based network), the method including: selecting a first network component of the NFV-based network, detecting at least one probable failure of the first network component, selecting a second network component to be used for replacing the instance of the VNF in the first network component prior to a failure of the first network component, and securing at least one resource of the selected second network component for the other instance of the VNF and maintaining, in the selected second network component, an updated copy of data associated with the instance of the VNF in the first network component.
Generating die block mapping after detected failure
A memory device includes a plurality of memory die blocks and a plurality of memory channels operably coupled to the plurality of memory die blocks and a memory controller configured to identify one or more memory die blocks as being invalid. The memory controller obtains a first matrix storing a mapping of memory channels to memory die blocks and creates a new mapping of memory channels to memory die blocks excluding the invalid memory die blocks. The new mapping is stored in a second matrix and one or more operations are performed on the memory die blocks based on the new mapping.