Execution of a store instruction to modify an instruction at a memory location identified by a memory address is requested. A cache controller stores the memory address and the modified data in an associative memory coupled to a data cache and an instruction cache. In addition, the modified data is stored in a second level cache without invalidating the memory location associated with the instruction cache.

A caching device, an instruction cache, a system for processing an instruction, a method and apparatus for processing data and a medium are provided. The caching device includes a first queue, a second queue, a write port group, a read port, a first pop-up port, a second pop-up port and a press-in port. The is configured to write cache data into a set storage address in the first queue and/or the second queue; the read port is configured to read all cache data from the first queue and/or the second queue at one time; the press-in port is configured to press cache data into the first queue and/or the second queue; the first pop-up port is configured to pop up cache data from the first queue; and the second pop-up port is configured to pop up cache data from the second queue.

A method and apparatus for snooping caches is disclosed. In one embodiment, a system includes a number of processing nodes and a cache shared by each of the processing nodes. The cache is partitioned such that each of the processing nodes utilizes only one assigned partition. If a query by a processing node to its assigned partition of the cache results in a miss, a cache controller may determine whether to snoop other partitions in search of the requested information. The determination may be made based on history of where requested information was obtained from responsive to previous misses in that partition.

A method of way prediction for a data cache having a plurality of ways is provided. Responsive to an instruction to access a stack data block, the method accesses identifying information associated with a plurality of most recently accessed ways of a data cache to determine whether the stack data block resides in one of the plurality of most recently accessed ways of the data cache, wherein the identifying information is accessed from a subset of an array of identifying information corresponding to the plurality of most recently accessed ways; and when the stack data block resides in one of the plurality of most recently accessed ways of the data cache, the method accesses the stack data block from the data cache.

Methods, systems, and devices for a split cache for address mapping data are described. A memory system may include a cache (e.g., including a first and second portion) for storing data that indicates a mapping between logical addresses associated with a host system and physical addresses of the memory system. The memory system may store data (e.g., the address mapping data) within the first portion of the cache. Additionally, the memory system may store an indication of whether the data is used for any access operations during a duration that the data is stored in the first portion of the cache. The memory system may transfer subsets of the data to the second portion of the cache if they are used for access operations during the duration.

Embodiments of the present disclosure relate to cache memory management. One or more global caches are dynamically partitioned and sized into one or more cache partitions based on anticipated input/output (IO) workloads.

The present technology relates to an electronic device. According to the present technology, a storage device having an improved operation speed may include a nonvolatile memory device, a main memory configured to temporarily store data related to controlling the nonvolatile memory device, and a memory controller configured to control the nonvolatile memory device and the main memory under control of an external host. The main memory may aggregate and process a number of write transactions having continuous addresses, among write transactions received from the memory controller, equal to a burst length unit of the main memory.

Systems and methods for supporting a plurality of load and store accesses of a cache are disclosed. Responsive to a request of a plurality of requests to access a block of a plurality of blocks of a load cache, the block of the load cache and a logically and physically paired block of a store coalescing cache are accessed in parallel. The data that is accessed from the block of the load cache is overwritten by the data that is accessed from the block of the store coalescing cache by merging on a per byte basis. Access is provided to the merged data.

A memory system is connectable to the host. The memory system includes a nonvolatile first memory, a second memory in which a plurality of pieces of first information each correlating a logical address indicating a location in a logical address space of the memory system with a physical address indicating a location in the first memory are stored, a volatile third memory including a first cache and a second cache, a compressor configured to perform compression on the plurality of pieces of first information, and a memory controller. The memory controller stores the first information not compressed by the compressor in the first cache, stores the first information compressed by the compressor in the second cache, and controls a ratio between a first capacity, which is a capacity of the first cache, and a second capacity, which is a capacity of the second cache.

A method and apparatus physically partitions clean and dirty cache lines into separate memory partitions, such as one or more banks, so that during low power operation, a cache memory controller reduces power consumption of the cache memory containing the clean only data. The cache memory controller controls a refresh operation so that a data refresh does not occur for the clean data only banks or the refresh rate is reduced for the clean data only banks. Partitions that store dirty data can also store clean data; however, other partitions are designated for storing only clean data so that the partitions can have their refresh rate reduced or refresh stopped for periods of time. When multiple DRAM dies or packages are employed, the partition can occur on a die or package level as opposed to a bank level within a die.