Devices and techniques for managing hazards in a memory controller are described herein. The memory controller can receive a memory request that includes a base memory address. An index can be computed from the base memory address and a lookup, using the index, can be performed to find a lock. When the lock is found, the memory controller can store the memory request in a buffer that corresponds to the lock. In response to a signal to clear the lock, the memory controller removes the memory request from the buffer and performs the memory request.

A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to, in a first clock cycle, a pre-arbitration winner between a first memory access request and a second memory access request based on a first number of credits allocated to a first destination device and a second number of credits allocated to a second destination device. The arbiter circuit is further configured to, in a second clock cycle select a final arbitration winner from among the pre-arbitration winner and a subsequent memory access request based on a comparison of a priority of the pre-arbitration winner and a priority of the subsequent memory access request.

An apparatus is configured to collect information related to a first activity and analyze the collected information to determine decision data. The information is stored in a first list of the source processing core for scheduling execution of the activity by a destination processing core to avoid cache misses. The source processing core is configured to transmit information related to the decision data using an interrupt, to a second list associated with a scheduler of the destination processing core, if the destination processing core is currently executing a second activity having a lower priority than the first activity.

A device includes an arbiter circuit configured to receive a first request for a resource. The first request is associated with a first credit cost. The arbiter circuit is further configured to receive a second request for the resource. The second request is associated with a second credit cost. The arbiter circuit is further configured to select the first request for the resource as an arbitration winner. The arbiter circuit is further configured to decrement a number of available credits associated with the resource by the first credit cost. The arbiter circuit is further configured to, in response to the number of available credits associated with the resource falling to a lower credit threshold, wait until the number of available credits associated with the resource reaches an upper credit threshold to select an additional arbitration winner for the resource.

An electronic device includes a cache, a processing cluster having one or more processors, and prefetch throttling circuitry that determines a congestion level of the processing cluster based on an extent to which the data retrieval requests sent from the processors to the cache are not satisfied by the cache. Congestion criteria require that the congestion level of the cluster is above a cluster congestion threshold. In accordance with a determination that the congestion level of the cluster satisfies the congestion criteria, the prefetch throttling circuit causes one of the processors to limit prefetch requests to the cache to prefetch requests of at least a threshold quality. In accordance with a determination that the congestion level of the cluster does not satisfy the congestion criteria, the prefetch throttling circuit forgoes causing the processors to limit prefetch requests to the cache to prefetch requests of at least the threshold quality.

A method of partitioning a set-associative cache for a plurality of software components may comprise identifying a cache height equal to a number of sets in the set-associative cache based on hardware specifications of a computing platform. The method may further comprise determining at least one component demand set of the plurality of software components and dedicating a set in the set-associative cache for the at least one component demand set. The method may further comprise assembling a proportional component sequence of the at least one component demand set having a sequence length equal to an integer submultiple of the cache height. The method may further comprise concatenating assembled proportional component sequences to form a template for mapping a RAM to the dedicated sets in the set-associative cache.

Various embodiments mitigate busy time in a hierarchical store-through memory cache structure including a cache directory associated with a memory cache. The cache directory is divided into a plurality of portions each associated with a portion of memory cache. A determination is made that a first subpipe of a shared cache pipeline comprises a non-store request. The shared pipeline is communicatively coupled to the plurality of portions of the cache directory. A store command is prevented from being placed in a second subpipe of the shared cache pipeline based on determining that a first subpipe of the shared cache pipeline comprises a non-store request. Simultaneous cache lookup operations are supported between the plurality of portions of the cache directory and cache write operations. Two or more store commands simultaneously processed in a shared cache pipeline communicatively coupled to the plurality of portions of the cache directory.

An optimized design of n-write/1-read port memory comprises a memory unit including a plurality of memory banks each having one write port and one read port configured to write data to and read data from the memory banks, respectively. The memory further comprises a plurality of write interfaces configured to carry concurrent write requests to the memory unit for a write operation, wherein the first write request is always presented by its write interface directly to a crossbar, wherein the rest of the write requests are each fed through a set of temporary memory modules connected in a sequence before being presented to the crossbar. The crossbar is configured to accept the first write request directly and fetch the rest of the write requests from one of the memory modules in the set and route each of the write requests to one of the memory banks in the memory unit.

N-way associative cache pools can be implemented in an N-way associative cache. Different cache pools can be indicated by pool values. Different processes running on a computer can use different cache pools. An N-way associative cache circuit can be configured to have one or more stripe mode cache pools that are N-way associative. A cache control circuit can receive a physical address for a memory location and can interpret the physical address as fields including a tag field that contains a tag value and a set field that contains a set value. The physical address can also be used to determine a pool value that identifies one of the stripe mode cache pools. A set of N cache entries in the one of the stripe mode cache pools can be concurrently searched for the tag value. The set of N cache entries is determined using the set value.

A client application cache access profile is created that documents accesses over time to data cached within an in-memory data grid (IMDG) cache by each of a set of client applications that utilize the IMDG. A new data request is received from one of the set of client applications that includes a client-application data caching vote that specifies whether the requesting client application wants the newly-requested data cached. In response to an IMDG cache data miss related to the new data request, a determination is made as to whether to cache the newly-requested data based upon analysis of the client application cache access profile of the client application from which the new data request was received, IMDG system performance cache costs of caching the newly-requested data, and the client-application data caching vote. The newly-requested data is cached within the IMDG cache in response to determining to cache the newly-requested data.