A memory device includes a page cache comprising a cache register, a memory array configured with a plurality of memory planes, and control logic, operatively coupled with the memory array. The control logic receives, from a requestor, a cache release command indicating that data associated with a first subset of the plurality of memory planes and pertaining to a previous read command was received by the requestor. Responsive to the cache release command, the control logic returns to the requestor, data from the cache register and associated with a second subset of the plurality of memory planes and pertaining to the previous read command, while concurrently copying data associated with the first subset of the plurality of memory planes and pertaining to a subsequent read command into the cache register.

A memory device includes a page cache comprising a cache register, a memory array configured with a plurality of memory planes, and control logic, operatively coupled with the memory array. The control logic receives, from a requestor, a first cache read command requesting first data from the memory array spread across the plurality of memory planes, and returns, to the requestor, data associated with a first subset of the plurality of memory planes and pertaining to a previous read command, while concurrently copying data associated with a second subset of the plurality of memory planes and pertaining to the previous read command into the cache register. The control logic further receives, from the requestor, a cache release command, and returns, to the requestor, the data associated with the second subset of the plurality of memory planes and pertaining to the previous read command, while concurrently copying data associated with the first subset of the plurality of memory planes and pertaining to the first cache read command into the cache register.

An arithmetic processing device includes an arithmetic circuit and a memory access controller performing access control for a read request on a memory module including a volatile memory and a nonvolatile memory, the volatile memory operating as a cache of the nonvolatile memory. The memory access controller stores an address table on which unit addresses including a request address of the read request are registered, issues a speculative read to the memory module in response to the read request and update the address table when the request address is included in the unit addresses in the address table, and issues a normal read when the request address is not included in any of the unit addresses. When the normal read is issued, read data is received after transmitting a transmission request signal. When the speculative read is issued, read data are acquired when receiving a hit flag.

In a data processor comprising a processing pass circuit and a cache, a record of processing passes to be performed by the processing pass circuit is stored, including storing, for each processing pass recorded in the buffer: information indicative of any data that is required for performing the processing pass that is not yet stored in the cache, including an identifier for any data that is required for performing the processing pass that is not yet stored in the cache. When new data to perform a processing pass is loaded into the cache, an identifier for that new data is compared to any identifiers for data that processing passes in the processing pass record are waiting for, and the information indicative of any data that is required for performing processing passes that is not yet stored in the cache stored in the processing pass record is updated.

A computer implemented method includes receiving a first request at a cache for first data and checking the cache for the first data. In response to the first data residing in the cache, the first data is provided from the cache. In response to the first data not residing in the cache, a first memory request is sent to memory for the first data, a first request pending bit to is set indicate the first request is pending, and the cache proceeds to process a next request for second data.

Systems and methods are disclosed including a processing device operatively coupled to memory device. The processing device perform operations comprising receiving a sequence of read commands from a memory sub-system controller; retrieving first data by executing a first read command of the set of read commands; storing the first data in a first portion of a cache of the memory device; responsive to determining that the memory device is in a suspended state, determining whether a first address range specified by the first read command overlaps with a second address range specified by a second read command of the set of read commands; responsive to determining that the first address range does not overlap with the second address range, retrieving second data by executing the second read command and storing the second data in a second portion of the cache; transferring the first and second data to the controller.

A memory device comprises: a page buffer including a first and second latch, a control circuit configured to perform reading data of a word line and storing the data in the first latch, perform discharging the word line, perform moving the data of the first latch to the second latch, and perform outputting the data of the second latch to an exterior, and a control logic configured to control the control circuit such that an execution section of the discharge and moving for a first word line at least partially overlap each other when a second or third cache read command is inputted in a section in which the storage or discharge for the first word line is performed in response to a first cache read command for the first word line.

Multi-cache-based digital output generation is provided. A system receives data objects that include fields from a remote data source. The system sorts the data objects based on a field to generate a sorted data set. The system cleans the sorted data set to generate a clean data set based on a policy. The system receives a request for a type of digital output based on the data objects received from the data source and loads a portion of the clean data set to a first level cache. The system selects a machine learning model configured for the type of digital output, and loads a primary cache with a subset of fields stored in the first level cache selected based on the machine learning model. The system generates, based on the first level cache being complete, digital output corresponding to the type of digital output from data in the primary cache.

Methods, systems, and devices for a latency indication in a memory system or sub-system are described. An interface controller of a memory system may transmit an indication of a time delay (e.g., a wait signal) to a host in response to receiving an access command from the host. The interface controller may transmit such an indication when a latency associated with performing the access command is likely to be greater than a latency anticipated by the host. The interface controller may determine a time delay based on a status of buffer or a status of memory device, or both. The interface controller may use a pin designated and configured to transmit a command or control information to the host when transmitting a signal including an indication of a time delay. The interface controller may use a quantity, duration, or pattern of pulses to indicate a duration of a time delay.

Multi-cache-based digital output generation is provided. A system receives data objects that include fields from a remote data source. The system sorts the data objects based on a field to generate a sorted data set. The system cleans the sorted data set to generate a clean data set based on a policy. The system receives a request for a type of digital output based on the data objects received from the data source and loads a portion of the clean data set to a first level cache. The system selects a machine learning model configured for the type of digital output, and loads a primary cache with a subset of fields stored in the first level cache selected based on the machine learning model. The system generates, based on the first level cache being complete, digital output corresponding to the type of digital output from data in the primary cache.