There is provided an apparatus that includes an input port to receive, from a requester, any one of: a lookup operation comprising an input address, and a maintenance operation. Maintenance queue circuitry stores a maintenance queue of at least one maintenance operation and address storage stores a translation between the input address and an output address in an output address space. In response to receiving the input address, the output address is provided in dependence on the maintenance queue. In response to storing the maintenance operation, the maintenance queue circuitry causes an acknowledgement to be sent to the requester. By providing a separate maintenance queue for performing the maintenance operation, there is no need for a requester to be blocked while maintenance is performed.

Techniques are disclosed relating to retrieving data from an in-memory cache, such as that for a database system. In various embodiments, an in-memory cache receives a request from an application for data, where the request specifies a class having a function executable to access the data from a location external to the cache in response to a cache miss. The cache handles the request such that the cache miss is not returned to the application. Specifically, the cache, in some embodiments, determines whether it stores the requested data, and in response to determining that it does not store the data, calls the function of the class to access the data from the location external to the cache and receives the data returned by the execution of the function. The cache then stores the received data in the cache and returns the received data in response to the request.

A request to access data at a first physical address misses in a private cache of a processor. A confidence value is received for the first physical address based on a hash value of the first physical address. A determination is made that the received confidence value exceeds a threshold value. In response, a speculative read request specifying the first physical address is issued to a memory controller of a main memory to expedite a miss for the data at the first physical address in a shared cache.

The present disclosure relates to a cache memory and methods that handle data forwarding from the cache memory to an action block to perform an action on the data. The action block performs an action on the data and outputs modified data in response to performing the action. The cache memory and methods use a latency parameter for data forwarding to prevent data hazards from occurring and to meet timing requirements and performance requirements of the cache memory.

A First-In-First-Out (FIFO) system and a method for providing access to a memory shared by a plurality of N clients are provided. The memory has a single memory space for holding a plurality of data storage arrays that are respectively configured to store data in a first-in-first-out manner for corresponding clients among the N clients. An arbiter is configured to receive memory access requests from two or more of the N clients to perform a FIFO operation, to push data into a corresponding storage array or to pop data from the corresponding storage array in response to the memory access request. The arbiter is configured to select a first at least one of the clients to perform a first FIFO operation in a first memory operation cycle and to select a second at least one of the clients to perform a second FIFO operation in a second memory operation cycle.

Technology for providing data to a processing unit is disclosed. A computer processor may be divided into a master processing unit and consumer processing units. The master processing unit at least partially decodes a machine instruction and determines whether data is needed to execute the machine instruction. The master processing unit sends a request to memory for the data. The request may indicate that the data is to be sent from the memory to a consumer processing unit. The data sent by the memory in response to the request may be stored in local read storage that is close to the consumer processing unit for fast access. The master processing unit may also provide the machine instruction to the consumer processing unit. The consumer processing unit may access the data from the local read storage and execute the machine instruction based on the accessed data.

The disclosure relates to accessing memory content with a high temporal locality of reference. An embodiment of the disclosure stores the content in a data buffer, determines that the content of the data buffer has a high temporal locality of reference, and accesses the data buffer for each operation targeting the content instead of a cache storing the content.

Systems, apparatuses, and methods related to memory systems and operation are described. A memory system may be coupled to a processor, which includes a memory controller. The memory controller may determine whether targeting of first data and second data by the processor to perform an operation results in processor-side cache misses. When targeting of the first data and the second data result in processor-side cache misses, the memory controller may determine a single memory access request that requests return of both the first data and the second data and instruct the processor to output the single memory access request to a memory system via one or more data buses coupled between the processor and the memory system to enable processing circuitry implemented in the processor to perform the operation based at least in part on the first data and the second data when returned from the memory system.

A method of retiring cache lines from a response buffer array to an icache array of a processor including providing sequential addresses to the icache array and to a response buffer array during successive clock cycles, detecting a first address hitting the response buffer array during a first clock cycle, during a second clock cycle that follows the first clock cycle, performing a first zero clock retire to write a first cache line from the response buffer array to the icache array, and during the second clock cycle, bypassing a second address which is one of the sequential addresses. The second address is bypassed given the assumption that it will likely hit the response buffer array in a subsequent cycle. If the second address missed the response buffer array, the bypassed address is replayed with a slight time penalty, which is outweighed by the time savings of zero clock retires.

A simultaneous multithread (SMT) processor having a shared dispatch pipeline includes a first circuit that detects a cache miss thread. A second circuit determines a first cache hierarchy level at which the detected cache miss occurred. A third circuit determines a Next To Complete (NTC) group in the thread and a plurality of additional groups (X) in the thread. The additional groups (X) are dynamically configured based on the detected cache miss. A fourth circuit determines whether any groups in the thread are younger than the determined NTC group and the plurality of additional groups (X), and flushes all the determined younger groups from the cache miss thread.