A processing-in-memory includes: a memory; a register configured to store offset information; and an internal processor configured to: receive an instruction and a reference physical address of the memory from a memory controller, determine an offset physical address of the memory based on the offset information, determine a target physical address of the memory based on the reference physical address and the offset physical address, and perform the instruction by accessing the target physical address.

An apparatus, a method, and a computer program product are provided that provide confidential computing on virtual machines by securing input/output operations between a virtual machine and a device. The method includes receiving an input/output (I/O) transaction from an I/O device requesting data stored memory from a virtual machine. The I/O transaction includes a virtual memory address and a bus device function. The method also includes associating the I/O transaction with a key slot associated with the virtual machine and retrieving, using the key slot, an encryption key used to encrypt and decrypt the data. The method further includes retrieving the data located at a physical memory address in physical memory relating to the virtual memory address of the data being requested and decrypting, during a read operation, the data using the encryption key for I/O transmission. The method also includes transmitting the decrypted data to the I/O device.

Process isolation for a PIM device includes: receiving, from a process, a call to allocate a virtual address space where the process stores a PIM configuration context; allocating the virtual address space including mapping a physical address space including PIM device configuration registers to the virtual address space only if the physical address space is not mapped to another process's virtual address space; and programming the PIM device configuration space according to the configuration context. When a PIM command is executed, a translation mechanism determines whether there is a valid mapping of a virtual address of the PIM command to a physical address of a PIM resource, such as a LIS entry. If a valid mapping exists, the translation is completed and the resource is accessed, but if there is not a valid mapping, the translation fails and the process is blocked from accessing the PIM resource.

Cache logic generates a cache address from an input memory address that includes a first binary string and a second binary string. The cache logic includes a hashing engine configured to generate a third binary string from the first binary string and to form each bit of the third binary string by combining a respective subset of bits of the first binary string by a first bitwise operation, wherein the subsets of bits of the first binary string are defined at the hashing engine such that each subset is unique and comprises approximately half of the bits of the first binary string; and a combination unit arranged to combine the third binary string with the second binary string by a reversible operation so as to form a binary output string for use as at least part of a cache address in a cache memory.

A system includes a memory device, and a processing device, operatively coupled to the memory device, to perform operations including storing, on a volatile memory device, logical-to-physical (L2P) mapping data corresponding to sequentially written data, determining whether an L2P update criterion is satisfied, and in response to determining that the L2P update criterion is satisfied, updating an L2P mapping data structure based on the L2P mapping data. The L2P mapping data structure maintains an initial logical translation unit (LTU) of the sequentially written data, and a length of the sequentially written data from the initial LTU.

An apparatus includes circuitry couplable to a host system and a memory device. The circuitry is configured to determine whether a page table maintained on the circuitry includes a physical address of the memory device corresponding to a virtual address associated with a TLB fill request from the host system. Responsive to determining that the page table includes the physical address, the circuitry provides signaling indicative of a completion to the TLB fill request to the host system, prefetch a page of data at the physical address from the memory device using the physical address from the page table, and provide signaling indicative of the page of data to the host system.

Embodiments disclosed pertain to apparatuses, systems, and methods for Translation Lookaside Buffers (TLBs) that support virtualization and multi-threading. Disclosed embodiments pertain to a TLB that includes a content addressable memory (CAM) with variable page size entries and a set associative memory with fixed page size entries. The CAM may include: a first set of logically contiguous entry locations, wherein the first set comprises a plurality of subsets, and each subset comprises logically contiguous entry locations for exclusive use of a corresponding virtual processing element (VPE); and a second set of logically contiguous entry locations, distinct from the first set, where the entry locations in the second set may be shared among available VPEs. The set associative memory may comprise a third set of logically contiguous entry locations shared among the available VPEs distinct from the first and second set of entry locations.

This application discloses a memory protection method and a protection proxy control apparatus. In an example method, in response to determining that an accelerator or an input/output (I/O) device requests to access a system memory by using a direct physical address, the protection proxy control apparatus may obtain, based on an identifier of a data stream of the accelerator or the I/O device, permission information of a physical page table in which a physical address requested to be accessed by the data stream is located, and perform permission check on the memory access request based on the permission information.

A data storage device may include a nonvolatile memory apparatus and a controller. The controller may be configured to translate a logical address into a physical address when receiving a host command (such as a write command or a read command) including the logical address from a host device, to generate a pre-command including the physical address, to transmit the generated pre-command to the nonvolatile memory apparatus before completing one or more remaining operations of the operations used to process the host command, and to transmit a confirm command to the nonvolatile memory apparatus when the remaining operations are complete. The controller may perform the remaining operations and the transmission of the pre-command to the nonvolatile memory apparatus at the same time.

Interrupt messages are sent from an interrupt controller to respective processor cores and data synchronization is managed among the processor cores. Each processor core includes a pipeline that includes a plurality of stages through which instructions of a program are executed, where stored order information indicates whether a state of the pipeline is in-order or out-of-order; and circuitry for receiving interrupt messages from the interrupt controller and performing an interrupt action in response to a corresponding interrupt message after ensuring that the order information indicates that the state of the pipeline is in-order when each interrupt action is performed. Managing the data synchronization includes generating a first interrupt message at an issuing processor core in response to a synchronization related instruction executed at the issuing processor core; and receiving the first interrupt message at each receiving processor core in a set of one or more receiving processor cores.