A network interface controller (NIC) capable of efficient packet forwarding is provided. The NIC can be equipped with a host interface, a packet generation logic block, and a forwarding logic block. During operation, the packet generation logic block can obtain, via the host interface, a message from the host device and for a remote device. The packet generation logic block may generate a plurality of packets for the remote device from the message. The forwarding logic block can then send a first subset of packets of the plurality of packets based on ordered delivery. If a first condition is met, the forwarding logic block can send a second subset of packets of the plurality of packets based on unordered delivery. Furthermore, if a second condition is met, the forwarding logic block can send a third subset of packets of the plurality of packets based on ordered delivery.

An address translation capability in which a processor obtains an address to be translated, and translates the address from the address to the another address. The translating includes determining an attribute of the address to be translated, and based on the attribute being a first attribute, first information is selected to be used in translating the address. Further, based on the attribute being a second attribute, second information is selected to be used in translating the address. The selected information is used to translate the address to the another address. The another address indicates one memory location based on the selected information being the selected first information, and another memory location based on the selected information being the selected second information.

A compute server accomplishes physical address to virtual address translation to optimize physical storage capacity via thin provisioning techniques. The thin provisioning techniques can minimize disk seeks during command functions by utilizing a translation table and free list stored to both one or more physical storage devices as well as to a cache. The cached translation table and free list can be updated directly in response to disk write procedures. A read-only copy of the cached translation table and free list can be created and stored to physical storage device for use in building the cached translation table and free list upon a boot of the compute server. The copy may also be used to repair the cached translation table in the event of a power failure or other event affecting the cache.

A processor includes translation-lookaside buffer (TLB) and a mapping module. The TLB includes a plurality of entries, wherein each entry of the plurality of entries is configured to hold an address translation and a valid bit vector, wherein each bit of the valid bit vector indicates, for a respective address translation context, the address translation is valid if set and invalid if clear. The TLB also includes an invalidation bit vector having bits corresponding to the bits of the valid bit vector of the plurality of entries, wherein a set bit of the invalidation bit vector indicates to simultaneously clear the corresponding bit of the valid bit vector of each entry of the plurality of entries. The mapping module generates the invalidation bit vector.

Data units are stored in private caches in nodes of a multiprocessor system, each node containing at least one processor (CPU), at least one cache private to the node and at least one cache locations buffer {CLB} private to the node. In each CLB location information values are stored, each location information value indicating a location associated with a respective data unit, wherein each location information value stored in a given CLB indicates the location to be either a location within the private cache disposed in the same node as the given CLB, to be a location in one of the other nodes, or to be a location in a main memory. Coherence of values of the data units is maintained using a cache coherence protocol The location information values stored in the CLBs are updated by the cache coherence protocol in accordance with movements of their respective data units.

Systems and methods for batched storage hinting with fast guest storage allocation. An example method may involve: detecting, by a hypervisor, that storage has been released by a guest operating system and remains allocated to a virtual machine executing the guest operating system; accessing, by the hypervisor, one or more sets of storage blocks, wherein a set of the one or more sets comprises an identifier associated with the storage and is associated with the virtual machine; receiving, by a processing device executing the hypervisor, a request to allocate a storage block to the virtual machine; identifying, by the hypervisor, at least one storage block of the one or more sets that is associated with the virtual machine; and allocating the at least one storage block to the virtual machine.

A virtual-address cache module receives at least a portion of a virtual address and in response indicates a hit or a miss. A first cache structure stores only memory blocks with virtual addresses that are members of a set of multiple synonym virtual addresses that have all been previously received by the virtual-address cache module during the operating period, where each member of a particular set of multiple synonym virtual addresses translates to a common physical address, and a memory block with the common physical address is stored in at most a single storage location within the first cache structure. A second cache structure stores only memory blocks with virtual addresses that do not have any synonym virtual addresses that have been previously received by the virtual-address cache during the operating period.

Racks and rack systems to support a plurality of sleds are disclosed herein. A rack comprises an elongated support post and a plurality of support chassis. The elongated support post extends vertically. The plurality of support chassis are coupled to the elongated support post. Each support chassis of the plurality of support chassis is sized to house a corresponding sled of the plurality of sleds.

Methods for read after write forwarding using a virtual address are disclosed. A method includes determining when a virtual address has been remapped from corresponding to a first physical address to a second physical address and determining if all stores occupying a store queue before the remapping have been retired from the store queue. Loads that are younger than the stores that occupied the store queue before the remapping are prevented from being dispatched and executed until the stores that occupied the store queue before the remapping have left the store queue and become globally visible.

The present disclosure relates to one or more memory management techniques. In embodiments, one or more regions of storage class memory (SCM) of a storage array is provisioned as expanded global memory. The one or more regions can correspond to SCM persistent cache memory regions. The storage array's global memory and expanded global memory can be used to execute one or more storage-related services connected to servicing (e.g., executing) an input/output (IO) operation.