G06F12/124

FAULT TOLERANT CLUSTER DATA HANDLING
20220179790 · 2022-06-09 ·

The described technology is generally directed towards fault tolerant cluster data handling techniques, as well as devices and computer readable media configured to perform the disclosed fault tolerant cluster data handling techniques. Nodes in a computing cluster can be configured to generate wire format resources corresponding to operating system resources. A wire format resource can comprise a cache key and a hint information to locate data, such as a file, corresponding to the operating system resource. The wire format resource can be stored in a resource cache along with a pointer that points to the operating system resource. The wire format resource can also be provided to client devices. Nodes in the computing cluster can be configured to receive and process client instructions that include wire format resources, as well as to use hint information to re-allocate data associated with a wire format resource.

System-on-chip and acceleration method for system memory accessing

An acceleration technology for accessing system memory, which provides translation agent hardware that calculates the physical address of the system memory based on an access request issued from the device end. The translation agent hardware has a cache memory that stores information to speed up the calculation of the physical address. Each cache line corresponds to a last-recently used (LRU) index value, and the cache line with the greatest LRU index value is preferentially released to be reassigned. A counter counts a count value to show an isochronous caching demand. LRU index values of cache lines assigned to non-isochronous caching are kept not lower than the count value, and thereby isochronous caching takes precedence over non-isochronous caching.

Memory system and operating method thereof
11334272 · 2022-05-17 · ·

A memory system includes: a memory device including memory blocks for storing data; and a controller suitable for controlling the memory device to increase a first read count for a logical address in a read command corresponding to a read request received from a host, move first data indicated by the logical address from a first memory block to a second memory block among the memory blocks when the first read count is greater than a first threshold value, increase a second read count of the first memory block, and perform a read reclaim operation on the first memory block when the second read count is greater than a second threshold value.

DATA CACHING METHODS OF CACHE SYSTEMS
20220147464 · 2022-05-12 · ·

A cache system includes a cache memory having a plurality of blocks, a dirty line list storing status information of a predetermined number of dirty lines among dirty lines in the plurality of blocks, and a cache controller controlling a data caching operation of the cache memory and providing statuses and variation of statuses of the dirty lines, according to the data caching operation, to the dirty line list. The cache controller performs a control operation to always store status information of a least-recently-used (LRU) dirty line into a predetermined storage location of the dirty line list.

System for Improving Input / Output Performance
20220129395 · 2022-04-28 ·

In one embodiment, data communication apparatus includes a network interface including one or more ports for connection to a packet data network and configured to receive content transfer requests from at least one remote device over the network, a storage sub-system to be connected to local peripheral storage devices, and including at least one peripheral interface, and a memory sub-system including a cache and RAM, and processing circuitry to manage transfer of content between the remote device(s) and the local peripheral storage devices via the peripheral interface(s) and the cache, responsively to the content transfer requests, while pacing commencement of serving of respective ones of the content transfer requests responsively to a metric of the storage sub-system so that while ones of the content transfer requests are being served, other ones of the content transfer requests pending serving are queued in at least one pending queue.

Variable cache status for selected volumes within a storage system

A method for improving cache hit ratios for selected volumes within a storage system is disclosed. In one embodiment, such a method includes storing, in a cache of a storage system, non-favored storage elements and favored storage elements. The favored storage elements are retained in the cache longer than the non-favored storage elements. The method maintains a “non-favored” LRU list that contains entries associated with non-favored storage elements and designates an order in which the non-favored storage elements are evicted from the cache. The method also maintains one or more “favored” LRU lists that contain entries associated with favored storage elements and designate an order in which the favored storage elements are evicted from the cache. Each “favored” LRU list is associated with favored storage elements that have a different preferred residency time in the cache. A corresponding system and computer program product are also disclosed.

System and method for inline tiering of write data

A method, computer program product, and computer system for receiving, by a computing device, new data to write to a leaf. At least two timestamps of the leaf may be examined. It may be determined whether a time interval between the at least two timestamps of the leaf is greater than an age threshold. The new data may be written to a first tier storage device when the time interval between the at least two timestamps of the leaf is less than the age threshold; The new data may be written to a second tier storage device when the time interval between the at least two timestamps of the leaf is greater than the age threshold.

Information processing device and computer-readable recording medium having stored therein cache control program
11176050 · 2021-11-16 · ·

An information processing device includes: a cache memory; and a processor configured to: manage the number of times of reference to be used for deduplication control of a data block; store, among data blocks in the cache memory, a first management list in which the data block in which writing is requested and the number of times of reference is 1 is managed by a least recently used scheme, and, among the data blocks in the cache memory, a second management list in which the data block in which writing is requested and the number of times of reference is equal to or larger than 2 is managed by the LRU scheme; and in a case where a data block to be written is registered in the first management list when a write request is processed, maintain the data block registered in the first management list over the cache memory.

SYSTEM-ON-CHIP AND ACCELERATION METHOD FOR SYSTEM MEMORY ACCESSING
20220004505 · 2022-01-06 ·

An acceleration technology for accessing system memory, which provides translation agent hardware that calculates the physical address of the system memory based on an access request issued from the device end. The translation agent hardware has a cache memory that stores information to speed up the calculation of the physical address. Each cache line corresponds to a last-recently used (LRU) index value, and the cache line with the greatest LRU index value is preferentially released to be reassigned. A counter counts a count value to show an isochronous caching demand. LRU index values of cache lines assigned to non-isochronous caching are kept not lower than the count value, and thereby isochronous caching takes precedence over non-isochronous caching.

Integration of application indicated maximum time to cache for a two-tiered cache management mechanism

An indication of a maximum retention time in a cache comprising a first type of memory and a second type of memory for a first plurality of tracks is received from a host application, wherein no maximum retention time is indicated for a second plurality of tracks. In response to demoting a track of the first plurality of tracks from the first type of memory to the second type of memory, an adjustment of a first amount of time that the track is allowed to be retained in the second type of memory is based on a second amount of time the track has already been present in the first type of memory prior to being demoted from the first type of memory to the second type of memory.