Tiering data between storage media in a content aware storage system is provided. An aspect includes, for each metadata page (MP) of a plurality of MPs: storing a first copy of the MP in a high tier storage, a second copy in an intermediate tier storage, and a third copy in low tier storage. Upon determining, in response to monitoring available space in the high tier storage, usage of the high tier storage exceeds a threshold value, an aspect includes identifying a least recently used (LRU) MP, deleting the LRU MP from the high tier storage, and destaging active entries of a metadata journal for the LRU MP. An aspect further includes receiving a request to read one of the plurality of MPs and, upon determining one of the MPs is the LRU metadata page, an aspect includes reading MP from the intermediate tier storage.

In exemplary aspects of managing the ejection of entries of a coherence directory cache, the directory cache includes directory cache entries that can store copies of respective directory entries from a coherency directory. Each of the directory cache entries is configured to include state and ownership information of respective memory blocks. Information is stored, which indicates if memory blocks are in an active state within a memory region of a memory. A request is received and includes a memory address of a first memory block. Based on the memory address in the request, a cache hit in the directory cache is detected. The request is determined to be a request to change the state of the first memory block to an invalid state. The ejection of a directory cache entry corresponding to the first memory block is managed based on ejection policy rules.

A data storage device may include: a storage; a controller configured to control data input to, and output from, the storage in response to a request from a host device; and a second buffer memory. The controller may include a first buffer memory, and is configured to store write data, provided by the host device, in the first buffer memory in response to a write request of the host device, and move the write data, stored in the first buffer memory, into the second buffer memory or the storage based on an attribute of the write data.

A controller controls an operation of a semiconductor memory device. The controller includes a cache buffer, a request analyzer, and a cache controller. The cache buffer stores multiple cache data. The request analyzer generates request information including information on a size of read data to be read. The cache controller determines an eviction policy of the multiple cache data, based on the size of the read data in the request information.

The disclosure relates to a method for processing a memory and apparatus, an electronic device, and a computer-readable storage medium. The method includes acquiring reclaimable memory pages occupied by an application to be processed; acquiring an idle duration of the application to be processed for each reclaimable memory page; determining a duration threshold according to the idle durations for the reclaimable memory pages; and selecting from the reclaimable memory pages a memory page for which the idle duration exceeds the duration threshold and reclaiming the memory page. The above-mentioned method for processing a memory and apparatus, electronic device and computer-readable storage medium may minimize the adverse impact on each application, thereby maintaining the balance between reclaiming and operation of an application memory to be processed.

A memory page management method is provided. The method includes receiving a state-change notification corresponding to a state-change page, and grouping the state-change page from a list to which the state-change page belongs into a keep list or an adaptive LRU list of an adaptive adjusting list according to the state-change notification; receiving an access command from a CPU to perform an access operation to target page data corresponding to a target page; determining that a cache hit state is a hit state or a miss state according to a target NVM page address corresponding to the target page, and grouping the target page into the adaptive LRU list according to the cache hit state; and searching the adaptive page list according to the target NVM page address to obtain a target DRAM page address to complete the access command corresponding to the target page data.

A method and system of translating addresses is disclosed that includes receiving an effective address for translation, providing a processor and a translation buffer where the translation buffer has a plurality of entries, wherein each entry contains a mapping of an effective address directly to a corresponding real address, and information on a corresponding intermediate virtual address. The method and system further include determining whether the translation buffer has an entry matching the effective address, and in response to the translation buffer having an entry with a matching effective address, providing the real address translation from the entry having the matching effective address.

Embodiments of the present disclosure are directed towards a computing device having a cache memory device with a scrubber logic. In some embodiments, the scrubber logic controller may be coupled with the cache device, and may perform a selection for eviction from the cache device a portion of data stored in the cache device, based at least in part on one or more selection criteria, at a dynamically adjusted level of aggressiveness of the selection performance. The scrubber logic controller may adjust the level of aggressiveness of the selection performance, based at least in part on a determined time left to complete the selection performance at a current level of aggressiveness. Other embodiments may be described and/or claimed.

A processor may allocate a first buffer segment from a buffer pool. The first buffer segment may be configured with a first contiguous range of memory for a first data partition of a data table. The first data partition comprising a first plurality of data blocks. A processor may store the first plurality of data blocks in order into the first buffer segment. A processor may retrieve the target data block from the first buffer segment in response to a data access request for a target data block of the first plurality of data blocks.

Provided are a computer program product, system, and method for invoking demote threads on processors to demote tracks from a cache. A plurality of demote ready lists indicate tracks eligible to demote from the cache. In response to determining that a number of free cache segments in the cache is below a free cache segment threshold, a determination is made of a number of demote threads to invoke on processors based on the number of free cache segments and the free cache segment threshold. The determined number of demote threads are invoked to demote tracks in the cache indicated in the demote ready lists, wherein each invoked demote thread processes one of the demote ready lists to select tracks to demote from the cache to free cache segments in the cache.