Apparatuses, methods, systems, and program products are disclosed for managing storage of digital content. An eligibility module determines one or more content elements that are eligible for compression. A content element is determined to be eligible for compression based on one or more characteristics of the content element. A rate module determines a compression rate for each of the one or more content elements. The compression rate comprises an amount of compression to be applied to a content element. The amount of compression to be applied to the content element is determined as a function of one or more characteristics of the content element. A compression module compresses each of the one or more eligible content elements according to the determined compression rate.

Embodiments herein provide for avoiding address collisions in a memory device. In one embodiment, a memory controller includes a command scheduler operable to process a read-modify-write I/O command to a location in memory, to detect another I/O command to the same memory location while the read-modify-write I/O command is accessing the memory location, and to stall the other I/O command until the read-modify-write I/O command is complete while allowing a third I/O command to access the memory.

An approach is provided for optimizing application caching and locking. Features specifying an operating environment of an application are extracted. The features include actual and forecasted central processing unit usage and memory, disk, and network pressure. A pairwise set of class-based and method-based ASTs and the extracted features are input into a logical neural network. Symbolic feature vectors are generated for the features by establishing bounds and flattening the features. The symbolic feature vectors and the set of class-based and method-based ASTs are input into a stacked transformer having encoders and decoders. The encoders and decoders are trained on word or token distributions of code ASTs and operating environment bounds associated with the ASTs. Using the stacked transformer, code is generated for replacing a portion of a method represented by a method-based AST. The code adds or changes caching or locking in the application.

Data operations, requiring a lock, are batched into a set of operations to be performed on a per-core basis under a single lock. A Most Recently Used (MRU) listing is used to conduct a demotion scan using an MRU flush, a processor identification (ID), and a track change characteristic algorithm.

In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.

Embodiments herein provide for avoiding address collisions in a memory device. In one embodiment, a memory controller includes a command scheduler operable to process a read-modify-write I/O command to a location in memory, to detect another I/O command to the same memory location while the read-modify-write I/O command is accessing the memory location, and to stall the other I/O command until the read-modify-write I/O command is complete while allowing a third I/O command to access the memory.

Apparatuses and methods can be related to encoding traffic between a host and a deep learning accelerator (DLA). Traffic between a host can be encoded utilizing an autoencoder. Encoding traffic between a host and a DLA changes the bandwidth of the traffic. Changing the bandwidth of the traffic prevents the correlation between the bandwidth and the input from which the traffic is generated.

A host device includes a unit processor configured to generate a near data processing (NDP) request, a host expansion control circuit configured to receive the NDP request; and a local memory device configured to store data corresponding to the NDP request according to control by the expansion control circuit. In response to receiving the NDP request, the host expansion control circuit performs a request processing operation to perform a read or a write operation corresponding to the NDP request on the local memory device and performs a computation operation using the requested data corresponding to the NDP request.

Techniques for obfuscating and/or de-obfuscating data using bit-level shard masks are disclosed. Shard masks are generated. The shard masks are designed to shard a block of data into a number of shards for distribution and storage among a number of storage arrays. The shard masks shard the block of data at a bit-level granularity. The shard masks are applied to the block of data to generate the shards. The shards are then distributed among the storage arrays for storage on the storage arrays.

Apparatuses and methods can be related to encoding traffic between a host and a DLA. Traffic between a host can be encoded utilizing an autoencoder. Encoding traffic between a host and a DLA changes the bandwidth of the traffic. Changing the bandwidth of the traffic prevents the correlation between the bandwidth and the input from which the traffic is generated.