A distributed storage system comprises a first module and a second module. The first module processes read requests for an address range, to send to the second module. The first module receives an address associated with a read request for a data page stored on the second module. A method searches a table on the first module for a content-based signature of the data page based on the address and provides the data page from a first module read cache if the content-based signature is in the read cache, where content-based signatures in the table are associated with the address range.

Systems and methods relate to cost-aware cache management policies. In a cost-aware least recently used (LRU) replacement policy, temporal locality as well as miss cost is taken into account in selecting a cache line for replacement, wherein the miss cost is based on an associated operation type including instruction cache read, data cache read, data cache write, prefetch, and write back. In a cost-aware dynamic re-reference interval prediction (DRRIP) based cache management policy, miss costs associated with operation types pertaining to a cache line are considered for assigning re-reference interval prediction values (RRPV) for inserting the cache line, pursuant to a cache miss and for updating the RRPV upon a hit for the cache line. The operation types comprise instruction cache access, data cache access, prefetch, and write back. These policies improve victim selection, while minimizing cache thrashing and scans.

Systems and methods relate to cost-aware cache management policies. In a cost-aware least recently used (LRU) replacement policy, temporal locality as well as miss cost is taken into account in selecting a cache line for replacement, wherein the miss cost is based on an associated operation type including instruction cache read, data cache read, data cache write, prefetch, and write back. In a cost-aware dynamic re-reference interval prediction (DRRIP) based cache management policy, miss costs associated with operation types pertaining to a cache line are considered for assigning re-reference interval prediction values (RRPV) for inserting the cache line, pursuant to a cache miss and for updating the RRPV upon a hit for the cache line. The operation types comprise instruction cache access, data cache access, prefetch, and write back. These policies improve victim selection, while minimizing cache thrashing and scans.

A memory system capable of running a variety of different read retry sequences includes a memory controller that has a boot ROM with stored code for executing a read retry sequence. A non-volatile memory device such as a NAND flash includes a read retry register and receives command instructions including a read retry instruction from the memory controller and in response provides read data. A second non-volatile memory that is external to the NAND flash has a read retry table describing read retry sequence items that include a command, a read retry register address, and read retry data for updating the read retry register.

A data processing system includes an upper level cache memory and a lower level cache memory employing different replacement policies. The lower level cache memory provides a respective one of a plurality of counters for each of a plurality of cache lines in a particular congruence class. The lower level cache memory initializes a counter value for a cache line in the particular congruence class that was castout from the upper level cache memory based on an indication of whether the cache line was accessed in the upper level cache memory following installation in the upper level cache memory. The lower level cache memory selects a victim cache line from among the plurality of cache lines in the particular congruence class for eviction from the lower level cache memory by reference to counter values of the plurality of counters.

Methods, devices, and systems for virtual address translation. A memory management unit (MMU) receives a request to translate a virtual memory address to a physical memory address and searching a translation lookaside buffer (TLB) for a translation to the physical memory address based on the virtual memory address. If the translation is not found in the TLB, the MMU searches an external memory translation lookaside buffer (EMTLB) for the physical memory address and performs a page table walk, using a page table walker (PTW), to retrieve the translation. If the translation is found in the EMTLB, the MMU aborts the page table walk and returns the physical memory address. If the translation is not found in the TLB and not found in the EMTLB, the MMU returns the physical memory address based on the page table walk.

A data storage structure, comprising: a plurality of storage units, each comprising: a storage media; and a library executive configured to manage the storage media. The structure further comprises a buffer connected to a controller, the controller comprising: a host interface configured to receive the instruction from the host machine; an object aggregator configured to combine the plurality of data objects into a data segment; a persistent write buffer configured to store the data segment; a persistent map configured to identify a location of each of the plurality of objects in the data segment; an erasure coder configured to encode the data segment into an erasure code; a destager configured to transfer the data segment from the persistent write buffer to the storage media in a given storage unit; and a library controller configured to communicate with the library executive in the given storage unit.

An optimized design of n-write/1-read port memory comprises a memory unit including a plurality of memory banks each having one write port and one read port configured to write data to and read data from the memory banks, respectively. The memory further comprises a plurality of write interfaces configured to carry concurrent write requests to the memory unit for a write operation, wherein the first write request is always presented by its write interface directly to a crossbar, wherein the rest of the write requests are each fed through a set of temporary memory modules connected in a sequence before being presented to the crossbar. The crossbar is configured to accept the first write request directly and fetch the rest of the write requests from one of the memory modules in the set and route each of the write requests to one of the memory banks in the memory unit.

A processing device comprises a processing device cache and a cache controller. The cache controller initiates a cache line eviction process and determines determine an object liveness value associated with a cache line in the processing device cache. The cache controller applies the object liveness value to a cache line eviction policy and evicts the cache line from the processing device cache based on the object liveness value and the cache line eviction policy.

A processing device comprises a processing device cache and a cache controller. The cache controller initiates a cache line eviction process and determines determine an object liveness value associated with a cache line in the processing device cache. The cache controller applies the object liveness value to a cache line eviction policy and evicts the cache line from the processing device cache based on the object liveness value and the cache line eviction policy.