Method and system are disclosed for arbitration of parallel multi-event processing. In one embodiment, a parallel multi-event processing system includes a plurality of hardware components, where each hardware component in the plurality of hardware components is assigned with a unique range of addresses, a plurality of hardware engines, where the plurality of hardware engines are configured to access the plurality of hardware components, a controller configured to perform arbitration on one or more requested transactions among the plurality of hardware engines and the plurality of hardware components based on one or more hardware components in the plurality of hardware components to be accessed, and the plurality of hardware components, the plurality of hardware engines, and the controller are configured to perform the one or more requested transactions according to the arbitration.

To reduce a capacity of a buffer included in a memory controller for managing a replacement area of a memory. Replacement management information for managing a relationship between a predetermined data area of a memory and a replacement area corresponding to the data area is stored in the memory. A memory controller includes: a replacement management information buffer configured to hold part of the replacement management information. A replacement processing unit, in a case in which replacement has occurred in the memory for data related to an access command from a host computer to the memory, causes the replacement management information buffer to hold the replacement management information of a portion of the data for which the replacement has occurred.

Apparatus identifies a set of M output memory addresses from a larger set of N input memory addresses containing at least one non-unique memory address. A comparator block performs comparisons of memory addresses from a set of N input memory addresses to generate a binary classification dataset that identifies a subset of addresses from the set of input addresses, where each address in the subset identified by the binary classification dataset is unique within that subset. Combination logic units receive a predetermined selection of bits of the binary classification dataset and sort its received predetermined selection of bits into an intermediary binary string in which the bits are ordered into a first group identifying addresses belonging to the identified subset, and a second group identifying addresses not belonging to the identified subset. Output generating logic selects between bits belonging to different intermediary binary strings to generate a binary output identifying a set of output memory addresses containing at least one address in the identified subset.

A connection circuit couples a first circuit of a device to a bus configured to provide access to an addressable memory space of the device. The connection circuit receives an input address transmitted by the first circuit. The input address corresponds to an address in a first address range or a second address range of the addressable memory space. The addressable memory space further includes a third address range that is not addressable by the first circuit. The connection circuit compares the input address with a threshold address. In response to the comparison, the connection circuit generates a portion of an output address, the output address belonging to the second address range or the third address range of the addressable memory space. The portion of the output address is then supplied to the bus.

Methods, apparatus, systems, and articles of manufacture are disclosed to determine memory access integrity based on feedback from memory. An example apparatus includes an access reconstruction controller including an output, a first input configured to be coupled to memory, and a second input configured to be coupled to a memory signal generator; a comparator including a first input coupled to the output of the access reconstruction controller, a second input configured to be coupled to an arbiter, and an output configured to be coupled to the arbiter; and a data integrity monitor including an input coupled to the second input of the comparator and configured to be coupled to the arbiter and an output coupled to the output of the comparator and configured to be coupled to the arbiter.

In one embodiment, an apparatus includes: an accelerator to execute instructions; an accelerator request decoder coupled to the accelerator to perform a first level decode of requests from the accelerator and direct the requests based on the first level decode, the accelerator request decoder including a memory map to identify a first address range associated with a local memory and a second address range associated with a system memory; and a non-coherent request router coupled to the accelerator request decoder to receive non-coherent requests from the accelerator request decoder and perform a second level decode of the non-coherent requests, the non-coherent request router to route first non-coherent requests to a sideband router of the first die and to direct second non-coherent requests to a computing die. Other embodiments are described and claimed.

An embodiment of a semiconductor package apparatus may include technology to create a tracking structure for a memory controller to track a range of memory addresses of a persistent memory, identify a write request at the memory controller for a memory location within the range of tracked memory addresses, and set a flag in the tracking structure to indicate that the memory location had the identified write request. Other embodiments are disclosed and claimed.

Systems, apparatuses, and methods for performing run-time checking of access uniformity of vector memory access instructions are disclosed. A system includes a vector unit, a scalar unit, and a memory. The system performs a run-time check to determine if two or more threads of a wave have access uniformity to the memory prior to executing a vector memory access instruction for the wave on the vector unit. The system replaces the vector memory access instruction with a group of instructions responsive to determining that two or more threads of the wave have access uniformity to the memory. The group of instructions includes a scalar access instruction to memory followed by a cross-thread data sharing instruction. The scalar access instruction is executed on the scalar unit. Alternatively, the group of instructions can include a vector memory access instruction by only a single thread in each group having access uniformity.

A memory system may include: a memory device having a plurality of banks, each comprising a memory cell region including a plurality of memory cells, and a page buffer unit; and a controller suitable for receiving a write address and write data from a host, and controlling a write operation of the memory device, wherein the controller comprises: a page buffer table (PBT) comprising fields to retain the same data as the page buffer units of the respective banks; and a processor suitable for comparing the write data to data stored in a field of the PBT, corresponding to the write address, and controlling the memory device to write the write data or the data stored in the page buffer unit to memory cells selected according to the write address, based on a comparison result.

A computer system having reduced write latency and methods for use in computer systems for reducing write latency are provided. Processing circuitry of the computer system is configured to execute a volume filter driver (VFD) that can be switched between a fast termination (FT) mode of operations and a normal, or quiescent, mode of operations. When the processing circuitry receives input/output (IO) write requests to write data to memory while the VFD is in the FT mode of operations, the VFD causes metadata associated with received IO write requests to be written to a volume of memory while preventing actual data associated with received IO write requests from being written to the volume, thereby resulting in extremely fast FT mode operation. After the file has been written to the volume, the VFD enters the quiescent mode of operations during which the VFD passes all IO write requests to the volume.