A system-on-chip (SoC) to perform a deadlock control on a processor of the SoC, the SoC including the processor including a plurality of central processing unit (CPU) cores, a first bus connected to the processor, a graphic processing unit (GPU) connected to the first bus, a memory controller connected to the first bus, a second bus connected to the processor, an isolation cell including a logic circuit configured to retain a signal value input to the processor according to an isolation signal, and a deadlock controller connected to the first bus and the second bus. The deadlock controller is configured to isolate the processor, which is in a deadlock state, from the first bus by applying the isolation signal on the isolation cell, and to extract, via the second bus, state information of the isolated processor in the deadlock state.

A method and apparatus for handling outstanding interconnect transactions between a master device and an interconnect component. For example, a transaction intervention module coupled to an interconnect component and a master device of the interconnect component. The transaction intervention module is arranged to receive an indication of a functional state of the master device. If the master device is indicated as being in a faulty functional state the transaction intervention module is further arranged to determine whether any interconnect transactions initiated by the master device with the interconnect component are outstanding. If it is determined that at least one interconnect transaction initiated by the master device is outstanding, the transaction intervention module is arranged to finalise the at least one outstanding interconnect transaction with the interconnect component.

In an embodiment, an apparatus comprises: a first component to perform coherent operations; and a coherent fabric logic coupled to the first component via a first component interface. The coherent fabric logic may be configured to perform full coherent fabric functionality for coherent communications between the first component and a second component coupled to the coherent fabric logic. The first component may include a packetization logic to communicate packets with the coherent fabric logic, but not include coherent interconnect interface logic to perform coherent fabric functionality. Other embodiments are described and claimed.

An asynchronous interface according to the disclosure includes: a transmission circuit that transmits, with data of W bits as one word, the data on the one-word basis, and transmits an REQ signal whose value differs by one bit per transmission of the data of one word; a reception circuit including a reception buffer having a reception buffer word count of n (n is an integer of 4 or more), in which the reception circuit receives the data on the one-word basis, and transmits an ACK signal whose value differs by one bit per reception of the data of one word; a data signal line that has a bit width of W, and transfers the data from the transmission circuit to the reception circuit; an REQ signal line that has a bit width of log.sub.2(n) or more, and transfers the REQ signal from the transmission circuit to the reception circuit; and an ACK signal line that has a bit width of log.sub.2(n) or more, and transfers the ACK signal from the reception circuit to the transmission circuit.

A system-on-chip (SoC) to perform a deadlock control on a processor of the SoC includes a processor of the SoC including a plurality of central processing unit (CPU) cores, a first bus connected to the processor, a graphic processing unit (GPU) connected to the first bus, a memory controller connected to the first bus, a second bus connected to the processor, an isolation cell including a logic circuit configured to retain a signal value input to the processor according to an isolation signal, and a deadlock controller connected to the first bus and the second bus, the deadlock controller being configured to isolate the processor, which is in a deadlock state, from the first bus by applying the isolation signal on the isolation cell, and extract, via the second bus, state information of the isolated processor in the deadlock state.

Embodiments of the present invention provide a solution for managing inter-domain resource allocation in a Peripheral Component Interconnect-Express (PCIe) network. One processor among a plurality of link processors is elected as a management processor. The management processor obtains information about available resources of PCIe network. When a resource request from a request processor is received, the management processor allocates a resource of the available resources to the requesting processor. The management processor instructs one or more link processors to program one or more inter-domain NTBs through which the traffic between the allocated resource and the requesting processor is going to flow according to the memory address information of the allocated resource, to allow cross-domain resource access between the requesting processor and the allocated resource.

Embodiments herein describe a multi-chip device that includes multiple ICs with interconnected NoCs. Embodiments herein provided address translation circuitry in the ICs. The address translation circuitry establish a hierarchy where traffic originating for a first IC that is intended for a destination on a second IC is first routed to the address translation circuitry on the second IC which then performs an address translation and inserts the traffic back on the NoC in the second IC but with a destination ID corresponding to the destination. In this manner, the IC can have additional address apertures only to route traffic to the address translation circuitry of the other ICs rather than having address apertures for every destination in the other ICs.

A multiprocessor computer system includes a plurality of processor nodes and at least a three-tier hierarchical network interconnecting the processor nodes. The hierarchical network includes a plurality of routers interconnected such that each router is connected to a subset of the plurality of processor nodes; the plurality of routers are arranged in a hierarchy of n3 tiers (T.sub.1, . . . , T.sub.n); the plurality of routers are partitioned into disjoint groups at the first tier T.sub.1, the groups at tier T.sub.i being partitioned into disjoint groups (of complete T.sub.i groups) at the next tier T.sub.i+1 and a top tier T.sub.n including a single group containing all of the plurality of routers; and for all tiers 1in, each tier-T.sub.i1 subgroup within a tier T.sub.i group is connected by at least one link to all other tier-T.sub.i1 subgroups within the same tier T.sub.i group.