A first state of an interconnect protocol is entered. A particular signal is sent according to the protocol to a device over a link. During the first state, it is detected that a response to the particular signal is received in the first state. It is determined that the device supports a configuration mode outside the protocol based on the received response. The configuration mode is entered based on the response. One or more in-band configuration messages are sent within the configuration mode.

A circuit for coupling a field bus and a local bus. A field bus controller is equipped to send and receive process data over the field bus. A local bus controller is equipped to send and receive the process data over the local bus. A data management unit is connected to the field bus controller and the local bus controller. The data management unit is equipped to transfer the process data between field bus controller and local bus controller. A memory area connected to the data management unit for copying and storing the process data. A processor connected to the data management unit and connected to the memory area. The processor is equipped to set up the data management unit to copy the process data into the memory area and the processor is equipped to read out the process data copied in the memory area.

Provided are systems and methods for distributing ordering tasks in a computing system that includes master and target devices. In some implementations, a computing device is provided. The computing device may include a master device that is operable to initiate transactions. The computing device may further include a target device that is operable to receive transactions. In some implementations, the master device may be configured to transmit one or more transactions to the target device. The master device may further asynchronously indicate to the target device a number of transactions to execute. The master device may further asynchronously receive from the target device a number of transactions executed. The master device may then signal that at least one transaction from the one or more transactions it sent has completed.

A communication device (100) to transmit a first communication frame and also transmit a second communication frame having a lower priority than a priority of transmitting the first communication frame includes a communication arbitration unit (107) to acquire, when a transmission request for the first communication frame has occurred during transmission of the second communication frame, an allowed time of a time required before a master device starts receiving the first communication frame, a remaining time until completion of the transmission of the second communication frame, and a necessary time required before the master device starts receiving the first communication frame, and determine whether to continue the transmission of the second communication frame on the basis of the allowed time, the remaining time, and the necessary time that have been acquired.

A system-on-chip bus system includes a bus configured to connect function blocks of a system-on-chip to each other, and a clock gating unit connected to an interface unit of the bus and configured to basically gate a clock used in the operation of a bus bridge device mounted on the bus according to a state of a transaction detection signal.

A method includes receiving a group of logic signals to be sampled at a common sampling timing. Individual time delays, which individually align each of the logic signals to the common sampling timing, are selected for the respective logic signals in the group. Each of the logic signals is delayed by the respective selected individual time delay, and the entire group of the delayed logic signals is sampled at the common sampling timing.

A dynamic bus communication apparatus for an electrosurgical system includes a data wire, a clock wire, a first variable resistor coupled to the data wire, a second variable resistor coupled to the clock wire, an analog to digital converter (ADC), and a controller. The data wire is configured to transmit a data signal between a battery and an instrument powered by the battery. The clock wire is configured to transmit a clock signal between a battery and an instrument. The ADC is configured to sample the data signal and the clock signal at a substantially higher frequency than a frequency of the clock signal. The controller is configured to control a resistance of the first variable resistor and a resistance of the second variable resistor based on the digitally sampled data signal and the digitally sampled clock signal.

Disclosed herein is a semiconductor device including a processor that processes input data received via a bus and transmits the process input data as output data via the bus; an input/output data converter that receives the output data via the bus, converts the output data into transmit preGPIO data, and transmits the transmit preGPIO data to the bus; and a GPIO input/output unit that receives the transmit preGPIO data via the bus, converts the transmit preGPIO data into transmit GPIO data, and outputs the transmit GPIO data to at least one GPIO pad.