A data processing system includes a host and an accelerator. The host transmits, to the accelerator, input data together with data identification information based on a data classification criterion. The accelerator classifies the input data as any one of feature data, a parameter, and a bias based on the data identification information when the input data is received from the host, distributes the input data, performs pre-processing on the feature data, and outputs computed result data to the host or feeds the result data back so that computation processing is performed on the result data again.

An electronic device comprises a bridge configured to transfer data bus transactions from a transaction source domain having a first bus width to a transaction target domain having a second bus width less than the first bus width. The bridge comprises a first interface configured to receive a transaction from the transaction source domain, where the transaction has a first transaction burst length. A converter logic is configured such that when a transaction is received via the first interface, the converter logic splits the transaction into a plurality of second transactions each having a respective second transaction burst length, wherein the plurality of second transactions have the second bus width. A second interface is configured to send the plurality of second transactions to the transaction target domain.

In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may receive first data from a first device via a first two-wire interface (TWI) bus; provide the first data to a second device via a second TWI bus; receive a first arbitration request via an out of band arbitration process from a third device; provide first control information via an in band arbitration process to the first device via the first TWI bus; receive second data from an isolation device via a third TWI bus; provide the second data to the second device via the second TWI bus; receive a second arbitration request via the in band arbitration process from the first device via the first TWI bus; and provide second control information via the out of band arbitration process to the third device.

Data retrieved from a portion of a device is obtained at a transmission buffer through an input/output (IO) cell of the device. The data is provided from the transmission buffer to a receiving buffer through the IO cell. The data is obtained from the receiving buffer. Responsive to a detection of a first mismatch between the data retrieved from the portion of the device and the data obtained from the receiving buffer, a fault is determined to have occurred at one or more of the transmission buffer or the receiving buffer.

Aspects of the invention include computer-implemented methods, systems, and computer program products that assign a centralized event tag to each communication interface of a plurality of communication interfaces of a chip interconnected in a hierarchy through the communication interfaces to a plurality of chips in a multiprocessing system. A determination is performed of whether to accept or drop a message associated with an event received at one of the communication interfaces of the chip based on comparing a local centralized event tag with a received centralized event tag. The local centralized event tag is updated based on one or more advancing rules to maintain event synchronization between the chip and the plurality of chips.

A control component implements pipelined data processing operations in either of two timing domains bridged by a domain-crossing circuit according to one or more configuration signals that indicate relative clock frequencies of the two domain and/or otherwise indicate which of the two timing domains will complete the data processing operations with lowest latency.

A data bus subscriber and a method for processing data, wherein the data bus subscriber can be connected to a local bus, particularly a ring bus, and the data bus subscriber has an input interface, which can be connected to the local bus, for receiving first local bus data, an output interface, which can be connected to the local bus, for transmitting second local bus data, a processing component for synchronous processing of the first local bus data and/or data stored in a memory and for output of at least one control signal, a logic unit, which is adapted in order to modify a quantity of received first local bus data based on the control signal in order to generate the second local bus data to be transmitted, wherein the logic unit is further adapted for synchronous, delayed transmitting of the second local bus data via the output interface.

A signal receiver and an electronic apparatus including the same are disclosed. A signal receiver according to an embodiment of the present disclosure includes a first input interface to output a first type signal, second to fourth input interfaces to output the first type signal or the second type signal, a first buffer electrically connected to the first and the second input interfaces, a second buffer electrically connected to the second and the third input interfaces, a third buffer electrically connected to the third and the fourth input interfaces, and a fourth buffer electrically connected to the fourth and the second input interfaces. Accordingly, it is possible to simply implement a circuit for receiving a plurality of types of signals.

In providing USB communication functionality over a non-USB-compliant extension medium, increased latency and processing delays may be introduced, including during configuration of endpoints. In some embodiments of the present disclosure, an upstream facing port device (UFP device) and a downstream facing port device (DFP device) are used to extend USB communication across an extension medium. In some embodiments, the UFP device extracts information from packets sent between a host device and a USB device during configuration of an endpoint. In some embodiments, the UFP device sends a synthetic NRDY packet to the host device in response to a STATUS Transaction Packet to provide the UFP device and DFP device additional time to complete configuration for servicing the endpoint.

Embodiments herein describe techniques for preventing a stall when transmitting data between a producer and a consumer in the same integrated circuit (IC). A stall can occur when there is a split point and a convergence point between the producer and consumer. To prevent the stall, the embodiments herein adjust the latencies of one of the paths (or both paths) such that a maximum latency of the shorter path is greater than, or equal to, the minimum latency of the longer path. When this condition is met, this means the shortest path has sufficient buffers (e.g., a sufficient number of FIFOs and registers) to queue/store packets along its length so that a packet can travel along the longer path and reach the convergence point before the buffers in the shortest path are completely full (or just become completely full).