A motherboard supply circuit includes a motherboard and a control circuit coupled to the motherboard. The motherboard is configured to couple to a power supply. The power supply is configured to supply power to a notebook computer and charge a battery. The power supply is also configured to supply power to the motherboard via the control circuit. The motherboard is configured to switch off the control circuit when detecting the notebook computer is in stand-by, thereby enabling the power supply not to supply power to the motherboard. The motherboard is also configured to switch on the control circuit upon detecting that the battery needs to be charged, thereby stopping the power supply from supplying power to the motherboard.

To provide an information processing device which is capable of suppressing corrosion of a terminal to which a cable or the like is connected, and which is novel and improved.

There is provided an information processing device including a voltage detection unit configured to monitor a voltage value of a signal output at a predetermined timing, and a signal control unit configured to stop output of the signal if the voltage value after a predetermined time elapses from when the voltage value detected by the voltage detection unit exceeds a first value does not exceed a second value greater than the first value.

A data pipeline circuit includes an upstream interface circuit that receives sequential data and a downstream interface circuit that transfers the sequential data to a downstream circuit. A ready signal indicates the downstream circuit is ready to receive the sequential data. The data pipeline circuit includes a first data latch, a second data latch and a first status latch. The first data latch receives the sequential data. The first status latch generates an available signal that is asserted to indicate the second data latch is available to receive the sequential data. The second data latch receives the sequential data in response on the available signal being asserted and the ready signal indicating the downstream circuit is not ready to receive the sequential data on the data output. Limiting conditions in which the sequential data is stored in the second data latch significantly reduces power consumption of the data pipeline circuit.

A low voltage drive circuit includes a transmit digital to analog circuit (DAC), a receive analog DAC and a drive sense circuit configured to receive transmit digital data. The transmit DAC is configured to convert transmit digital data into an analog outbound data signal and the receive analog DAC is configured to convert an analog outbound data signal into an analog transmit signal. The drive sense circuit is configured to drive the analog transmit signal on to a bus coupled to the low voltage drive circuit as a signal that varies loading on the bus at a first frequency to represent the analog outbound data signal. The drive sense circuit is further configured to receive an analog receive signal from the bus at a second frequency, convert the analog receive signal into an analog inbound data signal, convert the analog inbound data signal into received digital data, and output the received digital data.

Composite interface circuit including bidirectional single-conductor bus, first switching circuit, and second switching circuit. Bidirectional single-conductor bus is coupled by first pull-up resistor (R1) with first direct current (“DC”) input current source having first voltage (V1). First switching circuit includes first transistor (T1) being coupled with first pull-up resistor (R1) and with bidirectional single-conductor bus. Second switching circuit includes second transistor (T2) being coupled by second pull-up resistor (R2) with second DC input current source having second voltage (V2). Second switching circuit further includes voltage divider coupling second transistor (T2) with bidirectional single-conductor bus. First and second switching circuits are respectfully configured for being coupled with first transmitter conductor (Tx1) and first receiver conductor (Rx1) of full duplex universal asynchronous data communication interface.

A moving wing waterfowl or migratory bird decoy including a decoy body constructed of a predetermined material with exterior ornamentation to simulate a live waterfowl or migratory bird, the decoy body being arranged in a predetermined orientation to simulate a waterfowl or migratory bird, the decoy body having a top and a bottom. The decoy has at least one decoy wing connected to the decoy body, the decoy wing being constructed and arranged to simulate the wing of a waterfowl or migratory bird. The decoy body is constructed and arranged of a particular plastic material to hyper-realistically resemble a waterfowl or migratory bird. The control and power module is plug and play software controllable. The decoy is mountable on a male type member post via a female type receptacle on the decoy body. The decoy has a biased stabilizer cord that also mimics the legs of the waterfowl or migratory bird.

Disclosed is a home bus system (HBS) circuit, applicable to home bus (HB) communication implemented using a Microchip chip. The circuit includes the Microchip chip, an HBS communication chip, a resistor, a capacitor, and a transistor, the Microchip chip includes a universal asynchronous receiver/transmitter (UART) input pin and a serial peripheral interface (SPI) output pin, and the HBS communication chip includes an input pin. The transistor has a base coupled to the SPI output pin and a first end of the capacitor, a collector coupled to a first end of the resistor and the input pin of the HBS communication chip, and an emitter grounded, wherein a second end of the resistor is coupled to a power supply, and a second end of the capacitor is grounded.

Charge transfer between gate terminals of sub-threshold current reduction circuit (SCRC) transistors and related apparatuses and methods are disclosed. An apparatus includes a first output terminal electrically connected to a pull-up gate terminal of at least one pull-up SCRC transistor and a second output terminal electrically connected to a pull-down gate terminal of at least one pull-down SCRC transistor. The apparatus also includes a first resistive path between a first input terminal and the first output terminal and a second resistive path between the second input terminal and the second output terminal. The apparatus further includes a charge transfer gate electrically connected between the first resistive path and the second resistive path.

A hardware device, inserted in a universal serial bus port of a computing device, is detected. A counter is set to an initial value of one. In response to determining that one or more device descriptors associated with the hardware device are not received by the computing device within a predetermined time period, the hardware device is prevented from discharging a high-voltage charge into the computing device by inhibiting the hardware device from storing the high-voltage charge in a capacitor of the hardware device.

In accordance with an embodiment, a system includes: a primary device configured to be connected to at least one secondary device via serial bus having a data wire and a clock wire. The primary device is configured to: provide a clock signal on the clock wire; and transmit a frame comprising control bits on the serial bus, wherein a number of control bits transmitted on the serial bus at at least one location of the frame indicates a format of the frame.