An electronic device randomly modifies a current profile of a logic circuit by using an auxiliary circuit. The logic circuit includes a first terminal coupled to a supply voltage terminal, a second terminal coupled to a reference voltage terminal and an output terminal configured to deliver a signal in a high state or a low state. The auxiliary circuit is coupled between the first terminal and the second terminal and is configured to randomly generate or not generate an additional current between the first terminal and the second terminal on each change of state of the signal on the output terminal.

A laser detector includes a latch and a semiconductor device including the same. The laser detector includes a latch configured to output an output signal and an inverted output signal and an initial value setting circuit configured to set an initial value of at least one of the output signal and the inverted output signal. The latch includes a first transistor controlled to be initially turned on by the initial value and a second transistor controlled to be initially turned off by the initial value. The second transistor has an active region having a lateral area that is greater than that of the first transistor.

An electronic device includes a logic circuit and an auxiliary circuit. The logic circuit includes a first terminal coupled to a supply voltage terminal, a second terminal intended coupled to a reference voltage terminal and an output terminal configured to deliver a signal in a high state or a low state. The auxiliary circuit is coupled between the first terminal and the second terminal and is configured to randomly generate or not generate an additional current between the first terminal and the second terminal on each change of state of the signal on the output terminal.

The invention provides a attack prevention method, including: obtaining a first running start condition configured for a cipher engine; configuring, according to the first running start condition, a second running start condition for a scrambling module disposed on the chip, where the second running start condition is used to enable the scrambling module to enter an operating state of generating power consumption and an electromagnetic wave in a process of starting, according to the first running start condition, the cipher engine to perform data encryption/decryption processing; controlling the scrambling module to start to run when the second running start condition is met, where the scrambling module generates the power consumption and the electromagnetic wave during running; and controlling the cipher engine to start when the first running start condition is met, so that the cipher engine starts to perform data encryption/decryption processing.

Information leaked from smart cards and other tamper resistant cryptographic devices can be statistically analyzed to determine keys or other secret data. A data collection and analysis system is configured with an analog-to-digital converter connected to measure the device's consumption of electrical power, or some other property of the target device, that varies during the device's processing. As the target device performs cryptographic operations, data from the A/D converter are recorded for each cryptographic operation. The stored data are then processed using statistical analysis, yielding the entire key, or partial information about the key that can be used to accelerate a brute force search or other attack.

Chip cards that are protected from unauthorized access to information and instructions stored in the chip card's chip by unauthorized persons using illicit devices that emulate chip readers to interrogate the chips in chip cards and obtain or download confidential data stored in the chips. The chip cards are disabled when not ready to be used, such that the chips cannot be accessed by illicit devices, thus protecting the chip card owner and/or issuer from potential losses.

A glitch detection circuit (200) is arranged detect a glitch on a digital supply (150) and comprises a glitch sense threshold generator (132), a path delay circuit (133) comprising two parallel paths, wherein the first path provides a first output of a slow signal path of the digital supply to be detected that is used as a positive glitch threshold signal (530) and the second path provides a second output of a slow signal path of the digital supply to be detected that is used as a negative glitch threshold signal (540). A comparator circuit (134) is arranged to compare the digital supply to be detected with the first output of a slow signal path and the second output of a slow signal path; wherein the output of the comparator circuit indicates a power glitch on the digital supply in response to the positive or negative glitch threshold signals.