A pixel driving circuit and driving method thereof, an array substrate and a display device. The pixel driving circuit can maintain a voltage difference between two terminals of a storage capacitor (Cst) when a gate line scanning is ended. The pixel driving circuit comprises a pixel thin film transistor (T0) and a storage capacitor (Cst), wherein a gate of the pixel thin film transistor (T0) is connected to a gate line, a first terminal of the pixel thin film transistor (T0) is connected to a data signal (Data), a second terminal of the pixel thin film transistor (T0) is connected to a first terminal of the storage capacitor and a second terminal of the storage capacitor (Cst) is grounded. The pixel driving circuit further comprises a follow module connected the first terminal of the storage capacitor (Cst), and configured to maintain a voltage difference between two terminals of the storage capacitor (Cst) when a gate scanning signal (Gate(n)) makes a transition from a high level to a low level, so as to enable the pixel electrode to obtain sufficient voltage thereby ensuring the display effect of the liquid crystal display.

An array substrate and a manufacturing method thereof, and a display panel including the array substrate and a driving method thereof are provided. Each of the sub-pixel units of the array substrate includes a first thin film transistor and a second thin film transistor; the first thin film transistor includes a first gate electrode, a first source electrode and a first drain electrode; the second thin film transistor includes a second gate electrode, a second source electrode and a second drain electrode; each of the sub-pixel unit further includes a first pixel electrode electrically connected to the first drain electrode, a second pixel electrode electrically connected to the second drain electrode; and the first pixel electrode and the second pixel electrode are disposed in different layers and insulated with each other.

A display device includes a display portion defining a display area and including a plurality of pixels, a scan driver disposed in a non-display area that is outside of the display area, and a plurality of scan connection lines. Each of the pixels is connected to a scan line from among a plurality of scan lines and a data line from among a plurality of data lines. The scan connection lines connect the scan driver to the scan lines. Each of the scan connection lines is connected to one of the scan lines through a contact hole disposed in at least one insulating layer, which is disposed between the scan lines and the scan connection lines in a cross-sectional view.

A display device includes a display portion defining a display area and including a plurality of pixels, a scan driver disposed in a non-display area that is outside of the display area, and a plurality of scan connection lines. Each of the pixels is connected to a scan line from among a plurality of scan lines and a data line from among a plurality of data lines. The scan connection lines connect the scan driver to the scan lines. Each of the scan connection lines is connected to one of the scan lines through a contact hole disposed in at least one insulating layer, which is disposed between the scan lines and the scan connection lines in a cross-sectional view.

A display device includes a display panel having a plurality of pixels respectively connected to a plurality of gate lines and a plurality of data lines, a gate driving circuit that outputs a plurality of gate signals to the plurality of gate lines, and a data driving circuit configured that outputs a plurality of data signals for driving the plurality of data lines. Each of the plurality of pixels includes a first sub-pixel configured to receive a corresponding data signal among the plurality of data signals in response to a first gate signal among the plurality of gate signals, and a second sub-pixel configured to receive a corresponding data signal among the plurality of data signals in response to the first gate signal, and reduce a voltage of the received data signal in response to a second gate signal among the plurality of gate signals. The second gate signal is a signal delayed by a 2×d×H time relative to the first gate signal (where each of d and H is a positive integer, H is a horizontal period, and d×H is a pulse width of first and second gate signals).

A liquid crystal display includes a plurality of data lines and a plurality of gate lines disposed on a substrate in horizontal and vertical directions, respectively, pixel electrodes formed at intersecting regions of the data lines and the gate lines, a plurality of erasing signal lines disposed parallel to the gate lines, first thin film transistors, each including a first source electrode connected to one data line, a first gate electrode connected to one gate line, and a first drain electrode connected to one pixel electrode, and second thin film transistors, each including a second drain electrode connected to the pixel electrode, a second gate electrode connected to the erasing signal line, and a second source electrode connected to a predetermined potential.

A gate driver according to an exemplary embodiment of the present inventive concept includes a pull-up-pull-down circuit configured to pull up a gate signal to a high level of a first clock signal in a first duration and configured to pull down the gate signal to a low level of the first clock signal in a second duration, and a pull-down boosting circuit configured to output a first off voltage to the pull-up-pull-down part in the second duration in response to a second clock signal.

The present invention provides a liquid crystal display panel comprising: a display area in which a display area in which an array of pixel units is disposed, each of the pixel unit at least comprises a blue sub-pixel; a plurality of scan lines for providing a plurality of scan signals to the pixel units; and a plurality of data lines for providing a plurality of data signals to the pixel units, wherein the blue sub-pixels of the pixel units in every two separated columns, which are separated by one column, are coupled to a first data line, and the first data line provides an identical data signal to the blue sub-pixels in a same line of the two separated columns. The present invention further provides a method for driving the liquid crystal panel and a liquid crystal display comprising the above mentioned liquid crystal panel.

The present invention has a pixel which includes a first switch, a second switch, a third switch, a first resistor, a second resistor, a first liquid crystal element, and a second liquid crystal element. A pixel electrode of the first liquid crystal element is electrically connected to a signal line through the first switch. The pixel electrode of the first liquid crystal element is electrically connected to a pixel electrode of the second liquid crystal element through the second switch and the first resistor. The pixel electrode of the second liquid crystal element is electrically connected to a Cs line through the third switch and the second resistor. A common electrode of the first liquid crystal element is electrically connected to a common electrode of the second liquid crystal element.

A gate driving circuit includes a shift register circuit and an auxiliary circuit which are disposed at different sides of a pixel array. The shift register circuit includes an (N−1)th shift register stage for generating an (N−1)th gate signal according to a first clock, an Nth shift register stage for generating an Nth gate signal according to a second clock, and an (N+1)th shift register stage for generating an (N+1)th gate signal according to a third clock. The auxiliary circuit includes a first transistor. The first transistor performs the signal voltage stabilization and level switching acceleration operations on the Nth gate signal according to the (N−1)th gate signal and the second clock.