The implementation of a superhigh-definition liquid crystal display device with a diagonal of 30 inches or more and a resolution of 100 ppi or more is facilitated. There is provided a direct-view-type liquid crystal display device that includes a display portion in which a plurality of pixels are placed in a matrix, the display portion whose diagonal is 30 inches or more, in which the resolution of the display portion is 100 pixels or more per inch, the plurality of pixels include first to fourth pixels, and one of the first to fourth pixels is an RG-type formed of a red subpixel and a green subpixel and another of the first to fourth pixels is a BH-type formed of a blue subpixel and a green, yellow, or white subpixel.

A display may have an array of pixels arranged in rows and columns. Each pixel may have a transistor for controlling the amount of output light associated with that pixel. The transistors may be thin-film transistors having active areas, first and second source-drain terminals, and gates. Gate lines may be used to distribute gate control signals to the gates of the transistors in each row. Data lines that run perpendicular to the gate lines may be used to distribute image data along columns of pixels. The gate lines may be connected to gate line extensions that run parallel to the data lines. The data lines may each overlap a respective one of the gate line extensions. Vias may be used to connect the gate line extensions to the gate lines. The gate line extensions may all have the same length.

A display panel includes a display unit with a first area and a second area, first gate lines on the first area and the second area that extend in a first direction in the first area and in a third direction in the second area, while sections extending in the first direction and in a second direction are repeated, and second gate lines on the second area that extend in the third direction while sections extending in the first direction and in the second direction are repeated. The second gate line includes a plurality of sub gate lines that extend in the second direction in the second area, and one end of each of the plurality of sub gate lines is connected to one end of each of the plurality of second gate lines.

A light emitting substrate, a light emitting motherboard, a method for obtaining a light emitting substrate, and a displaying device. The light emitting substrate comprises a substrate and multiple light emitting units, wherein the substrate is provided with a light emitting region and a bind region located on one side of the light emitting region; each light emitting unit comprises a light zone provided with at least one light emitting diode and a drive circuit provided with multiple pins, and the multiple light emitting units are arranged on the substrate in an array; a direction pointing from the light emitting region to the bind region is a first direction; and in the first direction, the drive circuit of at least one light emitting unit in the last row of the light emitting units is connected to an address line.

A method of synchronizing a driving module includes applying a plurality of original data enable (“DE”) signals to a plurality of timing controller of the driving module, respectively, generating a synch DE signal from the driving module based on the earliest signal among the original DE signals, and transferring the synch DE signal to the plurality of timing controllers in a cascade mode.

The present inventive concept relates to a display device improving a bright difference.

An exemplary embodiment of the inventive concept provides a display device, including a panel including a plurality of pixel areas having different widths, and a data driver supplying data signals having different voltages to the plurality of pixel areas in response to a same grayscale.

A display apparatus includes: a display panel including a first display area and a second display area; a first timing controller to control an operation of the first display area, generate a first reference clock signal, generate a first internal reference clock signal based on the first reference clock signal, and generate a first synchronization clock signal based on the first internal reference clock signal; and a second timing controller to control an operation of the second display area, receive the first reference clock signal, generate a second internal reference clock signal based on the first reference clock signal, and generate a second synchronization clock signal based on the second internal reference clock signal, wherein the first and second timing controllers are to be synchronized with each other based on the first reference clock signal, and exchange first data based on the first and second synchronization clock signals.

According to an aspect, a display device includes: a display panel that has a display area in which a plurality of pixels are arranged; a light source configured to illuminate the display area; a first control circuit configured to receive first signals corresponding to a first partial image to be displayed in a portion of the display area; and a second control circuit configured to receive second signals corresponding to a second partial image to be displayed in another portion of the display area. The light source has a plurality of light-emitting areas in each of which a light emission intensity is individually controllable. The first control circuit is configured to transmit lighting quantity information indicating the light emission intensity of each of the light-emitting areas to the second control circuit.

A display may have an array of pixels such as liquid crystal display pixels. The display may include short pixel rows that span only partially across the display and full-width pixel rows that span the width of the display. The gate lines coupled to the short pixel rows may extend into the inactive area of the display. Supplemental gate line loading structures may be located in the inactive area of the display to increase loading on the gate lines that are coupled to short pixel rows. The supplemental gate line loading structures may include data lines and doped polysilicon that overlap the gate lines in the inactive area. In displays that combine display and touch functionality into a thin-film transistor layer, supplemental loading structures may be used in the inactive area to increase loading on common voltage lines that are coupled to short rows of common voltage pads.

A method for controlling a frame rate of a display screen includes: determining a first area and a second area of a display screen; and scanning the first area at a first frame rate, and scanning the second area at a second frame rate, wherein the first frame rate is greater than the second frame rate.