The liquid crystal display device includes: a control circuit (5) configured to perform input correction for a plurality of pixels (i1 to i12, j1 to j12, and k1 to k12) in each one of blocks (Bi1, Bj1, and Bk1) of a display unit (2), the input correction performed separately for each local area; a first source driver (4a) electrically connected to an end of each one of data signal lines (S1 to S24) that correspond to the pixels; and a second source driver (4b) electrically connected to another end of each data signal line (S1 to S24), wherein the first and second source drivers (4a and 4b) drive the data signal lines (S1 to S24) based on the input correction.

A driving method includes driving a display panel at a first-frequency driving mode and a second-frequency driving mode. A first frequency of the first-frequency driving mode is lower than a second frequency of the second-frequency driving mode. In the first-frequency driving mode, a frame time includes a scanning section and a corresponding front and rear porch section immediately following the scanning section. The driving method further includes scanning sub-pixels of the display panel in the scanning section of the first-frequency driving mode, where in the front and rear porch section, the sub-pixels of the display panel are not scanned, and front and rear porch sections corresponding to at least part of a plurality of frames in the first-frequency driving mode include at least one compensation section. The method further includes providing a data signal to each data line of a plurality of data lines of the display panel in a compensation section of the at least one compensation section.

A display apparatus includes a display panel configured to display an image, and including a plurality of gate lines extending in a first direction, a plurality of data lines extending in a second direction crossing the first direction, and a plurality of pixel units electrically connected to the gate lines and the data lines, a gate driving circuit configured to output a gate signal to each of the gate lines, and a data driving circuit configured to output data signals to the data lines using a column inversion method and a dot inversion method. In the column inversion method, polarities of the data signals, applied to first and second consecutive data lines, are inverted with respect to each other, and in the dot inversion method, polarities of the data signals applied to a third data line are inverted in pixel units arranged on opposite sides of the third data line.

A display apparatus includes a display panel including a gate line and a data line, a controller generating a source output enable signal determining an output timing of a data voltage output to the data line, and a data driver including a signal changer, generating a final source output enable signal by using the source output enable signal, and randomly changing the output timing of the data voltage for each gate line by using the final source output enable signal.

A timing control circuit is provided to control a data voltage outputted to a pixel array of a display panel during a frame period to perform a polarity reversal every N scan lines, where N is a positive integer. The timing control circuit includes a receiver and an adjustment circuit. The receiver is configured to sequentially receive first display data and second display data for one data line of the display panel. The adjustment circuit is coupled to the receiver to adjust at least one of gray information of the second display data and charging time of the second display data according to a voltage polarity of the first display data and a voltage polarity of the second display data. A corresponding operation method of the timing control circuit is also provided.

A semiconductor device where delay or distortion of a signal output to a gate signal line in a selection period is reduced is provided. The semiconductor device includes a gate signal line, a first and second gate driver circuits which output a selection signal and a non-selection signal to the gate signal line, and pixels electrically connected to the gate signal line and supplied with the two signals. In a period during which the gate signal line is selected, both the first and second gate driver circuits output the selection signal to the gate signal line. In a period during which the gate signal line is not selected, one of the first and second gate driver circuits outputs the non-selection signal to the gate signal line, and the other gate driver circuit outputs neither the selection signal nor the non-selection signal to the gate signal line.

A display device and a driving method of the same are proposed, the display device including first and second display panels displaying one image in a division manner; first and second data drivers supplying data voltages to the first and second display panels, respectively; first and second scan drivers supplying scan signals to the first and second display panels, respectively; and first and second timing controllers controlling the first and second data drivers and the first and second scan drivers, respectively, wherein the first data driver latches a first data signal output from the first timing controller in a first direction and converts the first data signal to a first data voltage to be outputted, and the second data driver latches a second data signal output from the second timing controller in a second direction and converts the second data signal to a second data voltage to be outputted.

A semiconductor device with low power consumption is provided. The semiconductor device includes a controller, a register, and an image processing portion. The image processing portion is configured to process an image data using a parameter. The image processing portion receives an image data from a frame memory and receives a parameter from the register. The frame memory is configured to retain the image data while power supply is stopped. The register is configured to retain the parameter while the power supply is stopped. The controller is configured to control power supply to the register, power supply to the frame memory, and power supply to the image processing portion. The register includes a scan chain register. A transistor with which the scan chain register is configured includes an oxide semiconductor in a channel formation region.

A liquid crystal display includes: a display panel; a signal controller configured to receive an input image signal and an input control signal, output an output image signal and an output control signal, and determine a charge sharing between two or more data lines having voltages in the same polarity; and a data driver configured to convert, based on the output control signal, the image signal into data voltages to be supplied to the data lines connected to the pixels, the data voltages having positive levels and negative levels. The data driver is further configured to perform a first charge sharing by short-circuiting first and second data lines that are adjacent to each other, and a second charge sharing by short-circuiting third and fourth data lines having data voltages in the same polarity, wherein the first charge sharing and the second charge sharing may not temporally overlap with each other.

A display apparatus includes a latch circuit configured to generate a second data value from a first data value, wherein the bit count of the second data value is greater than the bit count of the first data value, a digital-analog converter configured to convert the second data value into gray scale voltages, an output buffer unit configured to amplify the current level of the gray scale voltages to generate data voltages, a data switch circuit configured to invert the polarity of the data voltages every frame, and a display panel including a plurality of pixels driven with the data voltages supplied from the data switch circuit in response to sequential application of gate signals.