A display device and data driver are provided. The display device includes a plurality of data drivers provided for a predetermined number of data lines in a plurality of data lines. The plurality of data drivers receive the serialized video data signal from the display controller, generate a modulated data timing signal whose period changes within the one frame period, and supply a gradation voltage signal to each of the predetermined number of data lines for each of data periods based on a data timing of the modulated data timing signal, each of data periods corresponding to the data timing of the modulated data timing signal.

A display device including: a display area including pixels connected to data lines and scan lines, the display area including a plurality of signal output lines connected to each of the scan lines through a contact; a data driver including a first data driving circuit at a side of the display area; a scan driver disposed at the side of the display area; and a timing controller, wherein the first data driving circuit includes: output buffers which respectively output data signals to first to k-th data lines (k is an integer greater than 2) of the data lines; and an output delay controller which transmits the data signals to the output buffers through first to k-th transmission lines, and controls delay times of the data signals output to the first to k-th transmission lines based on position information of a pixel row to which the data signals are supplied.

A display apparatus includes a display panel including a plurality of horizontal lines each including a plurality of pixels, a timing controller configured to output a polarity control signal representing a polarity corresponding to each of the plurality of horizontal lines and having a value inverted by n horizontal line units, and a source driver configured to generate a timing pulse signal sequentially representing a data charging time of each of the plurality of horizontal lines and to output a data voltage, having a polarity corresponding to each of the plurality of horizontal lines, to the display panel on the basis of the timing pulse signal. When a value of the polarity control signal is inverted, the source driver generates the timing pulse signal including a data charging time corresponding to a count value obtained by counting a number of horizontal lines after a polarity is inverted.

Provided is a display device including a display panel configured to display an image, a gate driving circuit connected to the display panel, a data driving circuit connected to the display panel, and a timing controller configured to control the gate driving circuit and the data driving circuit, in which the data driving circuit senses a gate signal output from the gate driving circuit, and a data output timing is controlled based on an operation of another device or a signal generated therefrom together with the sensed gate signal.

A display device capable of improving image quality is provided. A display device includes a plurality of pixel blocks in a display region. The pixel blocks each include a first circuit and a plurality of second circuits. The first circuit has a function of adding a plurality of pieces of data supplied from a source driver. The second circuit includes a display element and has a function of performing display in accordance with the added data. One pixel has a configuration including one second circuit and an component of the first circuit that is shared. When the first circuit is shared by a plurality of pixels, the aperture ratio can be increased.

Disclosed are a driving method of an array substrate and an array substrate. The driving method of the array substrate controls a data drive signal line to output a first polarity data drive signal in a first time period and output a second polarity data drive signal in a second time period alternately. In the first time period, the first polarity data drive signal is output to drive the first sub-pixels of each pixel group to make the first sub-pixel of each pixel group to be a first polarity. In the second time period, the second polarity data drive signal is output to drive the second sub-pixel of each pixel group to make the second sub-pixel of each pixel group to be a second polarity. Polarities of sub-pixels of each column are the same.

A semiconductor device includes a display device and a source driver. Each of a plurality of pixels included in the display device is supplied with a first data potential and a second data potential included in a range of a first potential or higher to a second potential or lower. The first data potential makes the pixel display an image with a first gray level. The pixel performs calculation with the first data potential and the second data potential to generate a third data potential. The third data potential makes the pixel display an image with a second gray level. A reference potential of the first data potential is an intermediate potential between the first potential and the second potential, and the gray level width that can be displayed by the second data potential is larger than the gray level width that can be displayed by the first data potential.

Provided is a data integrated circuit including: a data driving circuit, a shift register configured to output a plurality of latch clock signals, a latch configured to latch a plurality of image signals in response to the plurality of latch clock signals and output a plurality of digital image signals in response to a plurality of latch output signals, and a clock generator configured to divide a main clock signal into the plurality of latch output signals and output the plurality of divided latch output signals to the latch. At least two of the latch output signals are activated at different time intervals.

An output buffer is provided, which including an input circuit, output circuits, a first multiplexer, a second multiplexer and a demultiplexer. The input circuit is for generating a first control signal and a second control signal according to a feedback signal and an input signal. Each output circuit is controlled by a first gate signal and a second gate signal to provide a corresponding one of output signals. The first multiplexer is for providing the first control signal and the second control signal to one of the output circuits as the first gate signal and the second gate signal, respectively. The second multiplexer is for providing a first reference voltage and a second reference voltage as the first gate signal and the second gate signal, respectively, to other of the output circuits. The demultiplexer is for providing one of the output signals as the feedback signal.

A display driver includes an amplifier circuit that outputs an output current based on a differential signal indicating a difference between a gradation voltage corresponding to a video signal and an output voltage to a source line of a display panel, thereby supplying the output voltage to the source line. An output current detection circuit generates a minor current by copying the output current, and outputs an output current detection signal representing the mirror current. A failure determination circuit determines whether a failure is occurring or has occurred in the source line or not by comparing the level of the output current detection signal with a prescribed threshold value. The output current detection circuit includes a transistor that generates a mirror current by receiving the differential signal at a gate thereof, and a variable resistance that generates an output current detection signal upon receiving the generated mirror current.