A touch display control circuit, a control method, and an electronic device are provided. The touch display control circuit is configured to drive STN-LCD screens, TN-LCD screens and CSTN-LCD screens. The touch display control circuit includes a display driving circuit and a touch detection circuit. The display driving circuit includes a signal transmission line, multiple groups of signal selection circuits and a reference voltage generation circuit. The signal transmission line is configured to transmit a gate signal and a common signal. The signal selection circuit is configured to select a preset control voltage based on display control timing or touch control timing. The reference voltage generation circuit is configured to provide the preset control voltage. The touch detection circuit is connected to the signal selection circuit and is configured to perform touch detection based on the touch control timing.

A liquid crystal display apparatus including a gate driving circuit disposed on a liquid crystal display is provided. The apparatus further includes a data driving chip, disposed on the liquid crystal display panel, to apply data driving signals to data lines. The gate driving circuit includes a plurality of stages connected to one another in parallel. The odd-numbered stages of the stages each apply gate driving signals to odd-numbered gate lines of the gate lines, in response to a first clock signal and the even-numbered stages of the stages each apply the gate driving signals to even-numbered gate lines of the gate lines, in response to a second clock signal having an opposite phase from a phase of the first clock signal.

A display panel and driving method, and a display device are provided. The display panel includes a display region and a border region. The display region includes a plurality of data lines extending along a first direction. The border region includes a data output circuit, having an output end electrically connected to a data line. The data output circuit includes at least one demultiplexer and 2L first-demultiplexers, where L is a positive integer, and L1. Each demultiplexer group includes a plurality of second-demultiplexers. The plurality of second-demultiplexers share a group of clock signal buses, wherein a portion of the plurality of second-demultiplexers are connected with a portion of the group of clock signal buses, and a remaining portion of the plurality of second-demultiplexers are connected with a remaining portion of the group of clock signal buses.

A liquid crystal display apparatus including a gate driving circuit disposed on a liquid crystal display is provided. The apparatus further includes a data driving chip, disposed on the liquid crystal display panel, to apply data driving signals to data lines. The gate driving circuit includes a plurality of stages connected to one another in parallel. The odd-numbered stages of the stages each apply gate driving signals to odd-numbered gate lines of the gate lines, in response to a first clock signal and the even-numbered stages of the stages each apply the gate driving signals to even-numbered gate lines of the gate lines, in response to a second clock signal having an opposite phase from a phase of the first clock signal.

The invention provides a display circuit and a LCD having the display circuit. The display circuit includes a display unit, a level shifter, a timer controller, and scanning circuits. Each scanning circuit includes a first voltage stabilizing circuit including first and second field effect transistors. Source electrodes of the two transistors are connected to the level shifter. The scanning circuits send a first group of scanning signals to the display unit in sequence in a first period of time, and send a second group of scanning signals to the display unit in sequence in a second period of time. The timer controller sends a control signal to the level shifter in a time difference between the two groups of signals. The level shifter converts the control signal to a high level signal and sends it to the two transistors to enable the two transistors to be under reverse bias.

A display device includes: sub-pixels each including a memory block including memories; memory selection line groups each including memory selection lines electrically coupled to the memory blocks in the sub-pixels that belong to the corresponding row; a memory selection circuit configured to concurrently output memory selection signals to the memory selection line groups; a potential line; a conduction switch provided for at least one memory in the memory block on a one-to-one basis; and an operating-memory conduction circuit configured to output, to the conduction switch, an operation signal for determining whether to electrically couple or uncouple the potential line and the corresponding one memory. Each memory is capable of storing sub-pixel data therein when being coupled to the potential line. Each sub-pixel displays an image based on the sub-pixel data stored in one memory in the sub-pixel according to the memory selection line supplied with the memory selection signal.

A constant-current passive-matrix array includes a two-dimensional array of pixels. Rows of pixels are each connected in common to a row wire and to a row controller operable to select one of the row wires with a row-select signal. Columns of pixels are each connected in common to a column wire and to a column controller. The column controller provides received pixel values to different column-control circuits, each connected to a column wire. Each column-control circuit comprises constant-current sources and a constant-current-source selection circuit operable to individually and separately enable each of the constant-current sources in response to the pixel value with a constant-current-source selection signal. The outputs of the constant-current sources are electrically connected in parallel to a column wire and the constant-current sources together are operable to output a constant-current column-data signal in response to the constant-current-source selection signals. The array can be a display or display cluster.

The invention provides a display circuit and a LCD having the display circuit. The display circuit includes a display unit, a level shifter, a timer controller, and scanning circuits. Each scanning circuit includes a first voltage stabilizing circuit including first and second field effect transistors. Source electrodes of the two transistors are connected to the level shifter. The scanning circuits send a first group of scanning signals to the display unit in sequence in a first period of time, and send a second group of scanning signals to the display unit in sequence in a second period of time. The timer controller sends a control signal to the level shifter in a time difference between the two groups of signals. The level shifter converts the control signal to a high level signal and sends it to the two transistors to enable the two transistors to be under reverse bias.

There is provided a semiconductor device including (1) a first power source section that includes a first power source output terminal and a second power source output terminal that output voltages at mutually different voltage levels, (2) a first output section that includes a first output stage switch that is provided between the first power source output terminal and a first voltage output terminal, and a second output stage switch that is provided between the second power source output terminal and the first power source output terminal, and (3) a controller that performs ON/OFF control of the first output stage switch and the second output stage switch such that both the first output stage switch and the second output stage switch are in an OFF state over a predetermined period encompassing a point in time when a signal level of the first signal switches.

A target image can be analyzed determine a respective level of visual saliency for each of a plurality of information presented in the target image. At least a first sub-frame update for a display panel can be determined, the at least first sub-frame update providing at least a partial rendering of the target image on the display panel, the at least partial rendering of the target image providing the information presented in the target image that is determined to have a highest level of visual saliency from among the plurality of information. The at least first sub-frame update can be applied to the display panel.