There are an N.sup.+ layer connected to a source line SL and an N.sup.+ layer connected to a bit line BL at both ends of a Si pillar standing on a substrate in a perpendicular direction, a P.sup.+ layer connected to the N.sup.+ layer, a first gate insulating layer surrounding the Si pillar, a first gate conductor layer surrounding the first gate insulating layer and connected to a plate line PL, and a second gate conductor layer surrounding a gate HfO.sub.2 layer surrounding the Si pillar and connected to a word line WL. The voltages applied to the source line SL, the plate line PL, the word line WL, and the bit line BL are controlled to perform a data hold operation of holding a group of holes generated by an impact ionization phenomenon or a gate-induced drain leakage current inside a channel region of the Si pillar and a data erase operation of removing the group of holes from the channel region.

There are an N.sup.+ layer connected to a source line SL and an N.sup.+ layer connected to a bit line BL at both ends of a Si pillar standing on a substrate in a perpendicular direction, a P.sup.+ layer connected to the N.sup.+ layer, a first gate insulating layer surrounding the Si pillar, a first gate conductor layer surrounding the first gate insulating layer and connected to a plate line PL, and a second gate conductor layer surrounding a gate HfO.sub.2 layer surrounding the Si pillar and connected to a word line WL. The voltages applied to the source line SL, the plate line PL, the word line WL, and the bit line BL are controlled to perform a data hold operation of holding a group of holes generated by an impact ionization phenomenon or a gate-induced drain leakage current inside a channel region of the Si pillar and a data erase operation of removing the group of holes from the channel region.

A memory device includes a plurality of memory cells. A first memory cell of the plurality of memory cells includes a first write transistor includes a first write gate, a first write source, and a first write drain. A first read transistor includes first read gate, a first read source, a first read drain, and a first body region separating the first read source from the first read drain. The first read source is coupled to the first write source. A first capacitor has a first upper capacitor plate coupled to the first write drain and a first lower capacitor plate coupled to the first body region of the first read transistor.

A first impurity layer 101a and a second impurity layer 101b are formed on a substrate Sub at both ends of a Si pillar 100 standing in a vertical direction and having a circular or rectangular horizontal cross-section. Then, a first gate insulating layer 103a and a second gate insulating layer 103b surrounding the Si pillar 100, a first gate conductor layer 104a surrounding the first gate insulating layer 103a, and a second gate conductor layer 104b surrounding the second gate insulating layer 103b are formed. Then, a voltage is applied to the first impurity layer 101a, the second impurity layer 101b, the first gate conductor layer 104a, and the second gate conductor layer 104b to generate an impact ionization phenomenon in a channel region 102 by current flowing between the first impurity layer 101a and the second impurity layer 101b. Of generated electrons and positive holes, the electrons are discharged from the channel region 102 to perform a memory write operation for holding some of the positive holes in the channel region 102, and the positive holes held in the channel region 102 are discharged from one or both of the first impurity layer 101a and the second impurity layer 101b to perform a memory erase operation.

A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including a plurality of first transistors and at least one metal layer, where the at least one metal layer overlays the first single crystal layer, and where the at least one metal layer includes interconnects between the plurality of first transistors, the interconnects between the plurality of first transistors include forming first control circuits; a second level overlaying the at least one metal layer, the second level including a plurality of second transistors; a third level overlaying the second level, the third level including a plurality of third transistors, where the second level includes a plurality of first memory cells, the first memory cells each including at least one of the plurality of second transistors, where the third level includes a plurality of second memory cells, the second memory cells each including at least one of the plurality of third transistors, where at least one of the plurality of second memory cells is at least partially atop of the first control circuits, where the first control circuits are adapted to control data written to at least one of the plurality of second memory cells; and where the plurality of second transistors are horizontally oriented transistors.

A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including a plurality of first transistors and at least one metal layer, where the at least one metal layer overlays the first single crystal layer, and where the at least one metal layer includes interconnects between the plurality of first transistors, the interconnects between the plurality of first transistors include forming first control circuits; a second level overlaying the at least one metal layer, the second level including a plurality of second transistors; a third level overlaying the second level, the third level including a plurality of third transistors, where the second level includes a plurality of first memory cells, the first memory cells each including at least one of the plurality of second transistors, where the third level includes a plurality of second memory cells, the second memory cells each including at least one of the plurality of third transistors, where at least one of the plurality of second memory cells is at least partially atop of the first control circuits, where the first control circuits are adapted to control data written to at least one of the plurality of second memory cells; and where the plurality of second transistors are horizontally oriented transistors.

A memory device includes pages arranged in columns and each constituted by a plurality of memory cells on a substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each memory cell included in each of the pages are controlled to perform a page write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, and the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform a page erase operation of discharging the group of positive holes from inside the channel semiconductor layer. The first impurity layer of the memory cell is connected to a source line, the second impurity layer thereof is connected to a bit line, one of the first gate conductor layer or the second gate conductor layer thereof is connected to a word line, and the other of the first gate conductor layer or the second gate conductor layer thereof is connected to a first driving control line. In a page read operation, page data in a group of memory cells selected by the word line is read to sense amplifier circuits, and in at least one operation among the page write operation, the page erase operation, and the page read operation, a voltage applied to at least one of the source line, the bit line, the word line, or the first driving control line is controlled by a reference voltage generating circuit combined with a temperature-compensating circuit.

A semiconductor memory device includes: a peripheral circuit portion including an interconnection; first and second word line stacks that are spaced apart from each other over the peripheral circuit portion, the first and second word line stacks including word lines, respectively; an alternating stack of dielectric layers that are positioned over the peripheral circuit portion and disposed between the first and second word line stacks; a first contact plug penetrating the alternating stack to be coupled to the interconnection; a second contact plug coupled to the word lines of the first and second word line stacks; a first line-shape supporter between the first word line stack and the alternating stack, and extending vertically from the peripheral circuit portion; and a second line-shape supporter between the second word line stack and the alternating stack, and extending vertically from the peripheral circuit portion.

An example apparatus comprises an array of memory cells coupled to sensing circuitry including a first sense amplifier, a second sense amplifier, and a logical operation component. The sensing circuitry may be controlled to sense, via first sense amplifier, a data value stored in a first memory cell of the array, sense, via a second sense amplifier, a data value stored in a second memory cell of the array, and operate the logical operation component to output a logical operation result based on the data value stored in the first sense amplifier and the data value stored in the second sense amplifier.

An example apparatus comprises an array of memory cells coupled to sensing circuitry including a first sense amplifier, a second sense amplifier, and a logical operation component. The sensing circuitry may be controlled to sense, via first sense amplifier, a data value stored in a first memory cell of the array, sense, via a second sense amplifier, a data value stored in a second memory cell of the array, and operate the logical operation component to output a logical operation result based on the data value stored in the first sense amplifier and the data value stored in the second sense amplifier.