An electronic system includes a controller configured to detect a bank in a standby state for a write operation between a first bank and a second bank during a refresh operation period and output data for performing a post-write operation to the bank in the standby state for the write operation. The electronic system also includes an electronic device including the first and second banks. The electronic device is configured to latch the data in an input/output control circuit connected to the bank in the standby state for the write operation.

Methods, systems, and devices related to domain-based access in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory array may be organized according to domains, which may refer to various configurations or collections of access lines, and selections thereof, of different portions of the memory array. In various examples, a memory device may determine a plurality of domains for a received access command, or an order for accessing a plurality of domains for a received access command, or combinations thereof, based on an availability of the signal development cache.

A memory controller interfaces with a random access memory over a memory channel. A refresh control circuit monitors an activate counter which counts a rolling number of activate commands sent over the memory channel to a memory region of the memory. In response to the activate counter being above an intermediate management threshold value, the refresh control circuit only issue a refresh management (RFM) command if there is no REF command currently held at the refresh command circuit for the memory region.

An electronic device includes a memory having a plurality of memory rows and a memory refresh functional block that performs a victim row refresh operation. For the victim row refresh operation, the memory refresh functional block selects one or more victim memory rows that may be victims of data corruption caused by repeated memory accesses in a specified group of memory rows near each of the one or more victim memory rows. The memory refresh functional block then individually refreshes each of the one or more victim memory rows.

A memory module includes a memory device configured to receive a first refresh command from a host, and perform a refresh operation in response to the first refresh command during a refresh time, and a computing unit configured to detect the first refresh command provided from the host to the memory device, and write a first error pattern at a first address of the memory device during the refresh time.

An apparatus may include multiple address registers each storing an address signal and multiple counter circuits each storing a count value corresponding to an associated one of the address registers. The apparatus may include a first circuit cyclically selecting one of the address registers in response to a first signal, a second circuit selecting one of the address registers based on the count value of each of the counter circuits, and a third circuit activating a second signal when the first and second circuits select the same one of the address registers.

A computer-implemented method includes refreshing a set of memory channels in a memory system substantially simultaneously, each memory channel refreshing a rank that is distinct from each of the other ranks being refreshed. Further, the method includes marking a memory channel from the set of memory channels as being unavailable for the rank being refreshed in the memory channel. In one or more examples, the method further includes blocking a fetch command to the memory channel for the rank being refreshed in the memory channel.

A semiconductor memory device and a memory system are provided. The semiconductor memory device includes a fingerprint read signal generator configured to generate a fingerprint read signal in response to a refresh counting control signal, a memory cell array comprising a plurality of sub memory cell array blocks, a fingerprint output unit configured to receive data output from memory cells connected to one selected among a plurality of word lines and one selected among a plurality of bit lines of one among the plurality of sub memory cell array blocks in response to the fingerprint read signal to generate fingerprint data, and a pseudorandom number generator configured to perform a linear feedback shifting operation in response to an active command to generate sequence data, receive the fingerprint data in response to the fingerprint read signal, and generate the sequence data based on the fingerprint data.

A memory device includes a memory cell array having a plurality of memory cells connected to wordlines and bitlines, a target row refresh logic configured to perform a refresh operation on at least one of target rows of the memory cell array in response to a refresh management mode command, a weak pattern detector that is activated according to a register update bit value included in the refresh management mode command and that outputs a risk level for each of the target rows, and a mode register circuit that updates at least one mode register value according to the risk level.

A semiconductor memory apparatus includes an address generation circuit and an operation determination circuit. The address generation circuit generates a refresh target address that corresponds to a word line, among a plurality of word lines, the word line being adjacent to another word line in which row hammering has occurred. The operation determination circuit configured to generate an address matching information by comparing a row hammering address with the refresh target address.