A semiconductor memory device and a memory system are provided. The semiconductor memory device includes a memory cell array, a normal refresh row address generator, a hammer refresh row address generator, a refresh selection signal generator, and a selector. The normal and hammer refresh row address generators generates a normal refresh row address and a hammer refresh row address, respectively, in response to a refresh counting control signal. The refresh selection signal generator sequentially generates normal and hammer refresh selection signals in response to the refresh counting control signal. The selector selects the normal refresh row address or the hammer refresh row address in response to the normal and hammer refresh selection signals. A normal refresh operation and a hammer refresh operation are sequentially performed on a memory cell array block among plural memory cell array blocks in response to the refresh row address.

An operating method of a memory device, the method including, receiving a row address, determining whether an operating mode is a byte mode, counting up an access count value for the row address while ignoring a page bit, when the operating mode is the byte mode, selecting a target row hammer address among target row addresses using access count values for the target row hammer address, calculating a victim row address corresponding to the target row hammer address, and performing a target refresh operation on the victim row address.

A refresh control circuit includes: a counting bloom filter that includes N hash control logics, each of which performs a hash operation on input data and outputs an M-bit sequence and M counters, each of which corresponds to a bit of the M-bit sequence, and updates count values of corresponding counters indicated by values of the M-bit sequences obtained from the N hash logics by using an address of a row of the memory cells as the input data; a candidate row determiner that determines rows of the memory cells accessed in a predetermined period in which the count values of the corresponding counters are greater than a threshold value as candidate rows for a target refresh operation; and a target refresh controller that outputs target refresh signals for rows of the candidate rows adjacent to one or more target rows determined by the candidate row determiner.

An electronic device includes a memory having a plurality of memory rows and a memory refresh functional block that performs a victim row refresh operation. For the victim row refresh operation, the memory refresh functional block selects one or more victim memory rows that may be victims of data corruption caused by repeated memory accesses in a specified group of memory rows near each of the one or more victim memory rows. The memory refresh functional block then individually refreshes each of the one or more victim memory rows.

A memory device includes a memory cell array including a plurality of memory cells connected to a plurality of wordlines and a plurality of bitlines, a target row refresh logic circuit configured to select a target row address from among a plurality of target row addresses as a refresh row address based on victim point values, and perform a refresh operation on first memory cells of the plurality of memory cells connected to a wordline of the plurality of wordlines indicated by the refresh row address, a victim point table configured to store the victim point values for the target row addresses, and a victim point accumulator configured to receive a first row address from an external device, and accumulate a first victim point value for at least one target row address corresponding to the first row address during a unit time period.

A memory device may enforce compliance with a refresh command requirement in some examples. When a controller fails to comply with the refresh command requirement, the memory device may prevent the controller from accessing a memory array. The controller may regain access by providing one or more commands, such as a refresh command. In some examples, the memory may enforce compliance with a refresh command requirement responsive to a value written to the mode register. In some examples, the memory may enforce compliance with the refresh command requirement after an initialization operation has completed.

A memory system includes: a memory device suitable for providing row-hammer data to set refresh rates for adjacent word lines of a target word line, and performing a target refresh operation on one or more word lines corresponding to a first row-hammer address according to a first target refresh command; and a memory controller suitable for generating a plurality of sampling addresses by sampling an active address, generating a plurality of counting values by comparing the sampling addresses with the active address, calculating a plurality of adjacent addresses corresponding to the sampling addresses based on the counting values and the row-hammer data, and providing the adjacent addresses as the first row-hammer address with the first target refresh command.

Methods, systems, and devices related to data relocation via a cache are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). In some cases, the memory device may transfer data from a first address of the memory array to the signal development cache. The memory device may transfer the data stored in the signal development cache to a second address of the memory array based on a parameter associated with the first address of the memory array satisfying a criterion for performing data relocation.

A memory system includes: a plurality of memory chips each including a plurality of banks and each suitable for generating a tracking address by tracking a row-hammer risk of selected banks among the banks, encrypting the tracking address using an encryption key to output tracking information to a corresponding data bus of a plurality of data buses and performing a target refresh operation according to a row-hammer address transferred through a command/address bus; and a memory controller suitable for collecting the tracking information for the banks transferred through the plurality of data buses to generate and output the row-hammer address to the command/address bus.

A memory apparatus comprises: a sampling circuit for sampling an input address through a sampling method corresponding to a first selection signal among at least two sampling methods, a storage circuit for storing up to N number of addresses having different values among sampled addresses received from the sampling circuit, an arranging circuit for determining an output sequence of addresses stored in the storage circuit through an arranging method corresponding to a second selection signal among the two arranging methods, and setting, as a target address, an address outputted according to the output sequence, a selection control circuit for setting each of the first selection signal and the second selection signal based on a state of the storage circuit, and a refresh operation circuit for controlling a target refresh operation on a row of memory cells corresponding to the target address.