A flash memory lifespan is increased, using a simple process, while restricting an increase in cost. A flash memory management device includes a flash memory having data retaining areas, which retain data, and short-lived areas, which have the same cell structure as the data retaining areas and data retaining properties inferior to those of the data retaining areas, wherein data of the short-lived areas are confirmed by a controller, and data retained in the data retaining areas are refreshed in accordance with the confirmed data of the short-lived areas.

A semiconductor device may implement a command-over-data function on a multi-level signaling data bus architectures. The multi-level signaling data bus architecture may support a multi-level communication architecture that includes a plurality of channels each including conversion of M bitstreams to N multi-level signals, where M is greater than N. A bitstream includes a plurality of bits provided serially, with each bit of the bitstream provided over a period of time. The multi-level signaling data bus is adapted to transmit data using a first set of assigned states of the data bus, and to transmit commands using at least a second assigned state of the data bus.

A semiconductor memory includes a main memory area and a tag memory area. A plurality of memory groups are set in the main memory area and a plurality of flag bits are set in the tag memory area. Each of the plurality of memory groups has a corresponding relationship with one of the plurality of flag bit. The flag bit is at least configured to indicate whether at least one memory cell in the memory group has a specific state. The specific state includes an occupied state.

A memory device coupled to a memory controller and including a memory array and an access circuit is provided. The memory array includes a plurality of cells. Each of the cells is coupled to a word-line. The access circuit is coupled between the memory controller and the memory array. In a normal mode, the access circuit executes a refresh action for the cells which are coupled to at least one word-line in response to the memory controller outputting an auto-refresh command. In a standby mode, the access circuit selects one of the word-lines and determines whether to execute the refresh action for the cells coupled to the selected word-line according to the retention capability of the selected word-line at regular time intervals.

An electronic device includes a count signal generation circuit configured to increase one of the values of a weak cell count signal and an active count signal by comparing a weak cell address with an adjacent address generated from a row address, when an active operation is performed. The electronic device also includes a target refresh control circuit configured to latch the adjacent address based on the values of the weak cell count signal and the active count signal and to output the latched adjacent address as a target address for a refresh operation based on a target refresh signal.

A memory system includes: a memory controller suitable for generating a first target address by sampling an address according to an active command, and providing the active command, a precharge command, a normal refresh command, the address and the first target address, to a memory device; and the memory device suitable for generating a first target refresh command according to the precharge command and the address, and refreshing one or more word lines corresponding to the first target address according to the first target refresh command.

A semiconductor memory device includes: a memory cell region including a plurality of cell mats in each of which a plurality of rows are disposed, each row coupled to normal cells and row-hammer cells; a repair control circuit suitable for generating a pairing flag denoting whether a cell mat in which an active row corresponding to an active address is disposed, is repaired with another cell mat; and a refresh control circuit suitable for: selecting, when an active command is inputted, a sampling address based on first and second data read from the row-hammer cells of the active row, refreshing, when a target refresh command is inputted, one or more adjacent rows to a target row corresponding to the sampling address, and selectively refreshing, when the target refresh command is inputted, one or more adjacent rows to a paired row of the target row according to the pairing flag.

Apparatuses and methods for generating multiple row hammer address refresh sequences. An example apparatus may include an address scrambler and a refresh control circuit. The address scrambler may receive a first address, output a second address in response to a first control signal, and output a third address in response to a second control signal. The second address may physically adjacent to the first address and the third address may physically adjacent to the second address. The refresh control circuit may perform a refresh operation on the second address when the first control signal is active and perform the refresh operation on the third address when the second control signal is active.

A system can be designed with memory to operate in a low temperature environment. The low temperature memory can be customized for low temperature operation, having a gate stack to adjust a work function of the memory cell transistors to reduce the threshold voltage (Vth) relative to a standard memory device. The reduced temperature can improve the conductivity of other components within the memory, enabling increased memory array sizes, fewer vertical ground channels for stacked devices, and reduced operating power. Based on the differences in the memory, the memory controller can manage access to the memory device with adjusted control parameters based on lower leakage voltage for the memory cells and lower line resistance for the memory array.

An electronic device includes a memory having a plurality of memory rows and a memory refresh functional block that performs a victim row refresh operation. For the victim row refresh operation, the memory refresh functional block selects one or more victim memory rows that may be victims of data corruption caused by repeated memory accesses in a specified group of memory rows near each of the one or more victim memory rows. The memory refresh functional block then individually refreshes each of the one or more victim memory rows.