A flash memory lifespan is increased, using a simple process, while restricting an increase in cost. A flash memory management device includes a flash memory having data retaining areas, which retain data, and short-lived areas, which have the same cell structure as the data retaining areas and data retaining properties inferior to those of the data retaining areas, wherein data of the short-lived areas are confirmed by a controller, and data retained in the data retaining areas are refreshed in accordance with the confirmed data of the short-lived areas.

Examples of the present disclosure relate to a device, method, and medium storing instructions for execution by a processor for refreshing memory blocks of solid state memory through a temperature compensated refresh rate. Techniques discussed herein include a solid state memory to store data and a temperature sensor to identify a temperature of the solid state memory. The memory device with solid state memory also includes a memory controller that periodically refreshes memory blocks of the solid state memory at an adjustable refresh rate, wherein memory controller is to adjust the adjustable refresh rate based on the temperature of the solid state memory.

A system can be designed with memory to operate in a low temperature environment. The low temperature memory can be customized for low temperature operation, having a gate stack to adjust a work function of the memory cell transistors to reduce the threshold voltage (Vth) relative to a standard memory device. The reduced temperature can improve the conductivity of other components within the memory, enabling increased memory array sizes, fewer vertical ground channels for stacked devices, and reduced operating power. Based on the differences in the memory, the memory controller can manage access to the memory device with adjusted control parameters based on lower leakage voltage for the memory cells and lower line resistance for the memory array.

Managing a temperature of a memory element of an information handling system, the method comprising: identifying a lower temperature boundary of the memory element; determining an initial temperature of the memory element; determining whether the initial temperature is less than the lower temperature boundary; in response to determining that the initial temperature is less than the lower temperature boundary: performing a series of repeated burst refresh operations at the memory element; after performing the series of repeated burst refreshes operations, determining an updated temperature of memory element; determining whether the updated temperature is less than the lower temperature boundary; and in response to determining that the updated temperature is greater than the lower temperature boundary, performing a normal boot of the memory element.

A memory system may improve the endurance and performance of a plurality of memories included in the memory system mounted on a server system or a data processing system. For example, the memory system may throttle energy of a first memory using a second memory having a different characteristic from the first memory, control accesses to a memory region according to a refresh cycle, and control accesses to memories having different temperatures according to a priority of a request for each of the memories.

A temperature sensing circuit adapted for a memory device and including an oscillator, a count circuit, a control circuit, a sense circuit and a select circuit is provided. The oscillator provides an oscillation signal. The count circuit counts the oscillation signal to generate a first count signal, and generates a second count signal. The count circuit performs a logic operation on the second count signal to generate an enable signal and a sensing adjustment signal. The sense circuit generates a reference temperature voltage by dividing a reference voltage according to the sensing adjustment signal, and compares the reference temperature voltage and a monitor voltage according to the enable signal to generate a determination signal. The select circuit dynamically selects one of the oscillation signal and the first count signal according to the determination signal, and generates a pulse of a refresh request signal according to the dynamically selected one of the oscillation signal and the first count signal.

Memory bank remapping based on sensed temperatures of a memory device can provide an overall reduced power consumption of the memory device. Signaling indicative of sensed temperatures detected by a plurality of temperature sensors within a stack of memory dies of a memory device can be received by address circuitry of the memory device. Based on the sensed temperatures and respective positions of the temperature sensors within the stack of memory dies, a portion of the memory device experiencing an excessive operating temperature can be identified. Logical addresses of a first memory bank of a memory die of the stack of memory dies near or at least partially within the identified portion can be remapped to physical addresses of a second memory bank of the memory die that is further away from the identified portion than the first memory bank.

Methods, systems, and apparatus related to memory management based on temperature evaluation and a status of storage media availability (e.g., whether usage of the storage media exceeds a threshold). In one approach, the memory management is implemented in a memory device having first and second memories. A controller of the memory device evaluates data from a temperature sensor to determine that a temperature of the memory device exceeds a normal operating range. Based on this evaluation, the controller selects the first memory (e.g., SLC memory) for storing incoming data. If the first memory becomes full, the controller switches to the second memory (e.g., TLC or QLC memory) for storing additional incoming data. When the temperature returns to the normal operating range, the additional data is re-written while in the normal operating range.

One or more write operations are performed on a memory component. First data stored at the memory component is read. A determination is made as to whether an error rate associated with the first data stored at the memory component exceeds an error rate threshold. If the error rate exceeds the error rate threshold, a threshold value is adjusted. A determination is made as to whether a number of the plurality of write operations performed on the memory component since performance of a refresh operation on the memory component exceeds the threshold value. In response to determining that the number of write operations performed on the memory component exceeds the threshold value, a memory cell of the memory component is identified based on the plurality of write operations. Second data stored at memory cells of the memory component that are proximate to the identified memory cell is refreshed.

Structures including non-volatile memory elements and methods of forming such structures. The structure includes a first non-volatile memory element, a second non-volatile memory element, and temperature sensing electronics coupled to the first non-volatile memory element and the second non-volatile memory element.