A semiconductor memory device can appropriately control operation timing, based on changes in the environment (for example, power supply voltage and temperature, etc.) when in use. The semiconductor memory device includes a temperature sensor 18 that detects the temperature of the semiconductor memory device, a voltage detection portion (composed of a ring oscillator 14 and a counter 15) that detects the power supply voltage of the semiconductor memory device, and a control portion 10 that controls the operation timing in the semiconductor memory device to meet specific conditions, according to the temperature detected by the temperature sensor 18 after the power is applied and the voltage detected by the voltage detection portion after the power is applied.

A data processing system includes a first memory, a second memory, a temperature sensor, and a controller. The temperature sensor is configured to sense a temperature at the data processing system and generate a temperature signal. The controller is configured to control whether the first memory is enabled or disabled and whether the second memory is enabled or disabled based on the temperature signal and based on a first temperature threshold associated with the first memory and a second temperature threshold associated with the second memory.

One or more write operations are performed on a memory component. First data stored at the memory component is read. A determination is made as to whether an error rate associated with the first data stored at the memory component exceeds an error rate threshold. If the error rate exceeds the error rate threshold, a threshold value is adjusted. A determination is made as to whether a number of the plurality of write operations performed on the memory component since performance of a refresh operation on the memory component exceeds the threshold value. In response to determining that the number of write operations performed on the memory component exceeds the threshold value, a memory cell of the memory component is identified based on the plurality of write operations. Second data stored at memory cells of the memory component that are proximate to the identified memory cell is refreshed.

Apparatuses and methods of for refresh control of a semiconductor device are described. An example apparatus includes a command control circuit that provides a plurality of pulses on a first control signal in series responsive to a plurality of refresh commands issued in series; a signal generation circuit that produces a plurality of pulses on a second control signal in sequence; and a refresh control circuit that receives two or more of the plurality of pulses on the first control signal during a period of time between one pulse and a succeeding pulse of the plurality of pulses on the second control signal, disables refresh operations responsive to at least one of the two or more of the plurality of first control signal and executes a refresh operation responsive to remaining one or more pulses of the two or more of the plurality of pulses on the first control signal.

The present invention provides a memory controller including a decoder, an error bit counter and a refresh rate control circuit. The decoder is configured to receive and decode data from a memory module to generate decoded data. The error counter is coupled to the decoder, and is configured to generate error bit information of the data. The refresh rate control circuit is coupled to the error counter, and is configured to determine a refresh rate of the memory module according to the error bit information.

An information handling system includes a processor that runs a maximum memory stress test of a memory module with a refresh rate of memory devices set to a first refresh rate. Then, the processor may receive a power consumption of the memory module. Also, the processor may receive the temperature of the memory devices, and may set the refresh rate to a second refresh rate. The processor may continuously receive both the power consumption of the memory module and the temperature of the memory devices. Based on the continuously received temperature, the processor may determine whether the temperature of the memory devices exceeds a second threshold temperature. If so, the processor may store a first setting as a refresh setting for the memory module. Otherwise, the processor may store a second setting as the refresh setting for the memory module.

An aspect includes reading a plurality of sensor values from a plurality of sensors located on a plurality of memory dies in the HMC. It is determined that one of the plurality of sensor values from a sensor located on one of the plurality of memory dies has exceeded a threshold value. Based on the determining and on the one of the plurality of sensor values, calculating a refresh rate for the memory locations on the one of the plurality of memory dies. The vault controller is reconfigured to apply the calculated die refresh rate to the memory locations in the vault that are located on the one of the plurality of memory dies. The calculated die refresh rate is different than an other refresh rate being applied to memory locations in the vault that are located on an other one of the plurality of memory dies.

Disclosed herein is a semiconductor device that includes: a memory cell array including a plurality of memory groups each having a plurality of memory cells, the memory groups being selected by mutually different addresses; a first control circuit periodically executing a refresh operation on the memory groups in response to a first refresh command: and a second control circuit setting a cycle of executing the refresh operation by the first control circuit. The second control circuit sets the cycle to a first cycle until executing the refresh operation to all the memory groups after receiving the first refresh command, and the second control circuit sets the cycle, to a second cycle that is longer than the first cycle after executing the refresh operation to all the memory groups.

A semiconductor device is provided, including multiple memory chips and a temperature detection module. The temperature detection circuit includes: multiple temperature sensitive units, arranged on the memory chips to detect temperatures of the memory chips; and a processing unit. The multiple temperature sensitive units share the processing unit with each other. The processing unit is configured to process a signal of at least one of the temperature sensitive units. The processing unit includes a calibration value memory cell and a calibration unit. The calibration value memory cell is configured to store a calibration value corresponding to the temperature sensitive unit. The calibration unit is configured to calibrate the temperature sensitive unit according to the calibration value.

Disclosed herein is a device includes a command generation circuit that activates first and second command signals, an internal circuit that includes a plurality of transistors that are brought into a first operation state when at least one of the first and second command signals is activated, and an output gate circuit that receives a first signal output from the internal circuit, the output gate circuit being configured to pass the first signal when the second command signal is deactivated and to block the first signal when the second command signal is activated.