SRAM cells are connected in columns by bit lines and connected in rows by first and second word lines coupled to first and second data storage sides of the SRAM cells. First the first word lines are actuated in parallel and then next the second word lines are actuated in parallel in first and second phases, respectively, of an in-memory compute operation. Bit line voltages in the first and second phases are processed to generate an in-memory compute operation decision. A low supply node reference voltage for the SRAM cells is selectively modulated between a ground voltage and a negative voltage. The first data storage side receives the negative voltage and the second data storage side receives the ground voltage during the second phase. Conversely, the second data storage side receives the negative voltage and the first data storage side receives the ground voltage during the first phase.

An integrated circuit includes a diode for generating a temperature dependent voltage, a resistor divider for generating divided voltages by dividing the temperature dependent voltage, and a multiplexer circuit for selecting one of the divided voltages as a reference voltage used for setting a supply voltage.

The present application discloses an interface transformer. The interface transformer includes a first clock generator, a combinational circuit, and a second clock generator. The first clock generator generates an intermediate clock signal according to an input clock signal. A rising edge of the input clock signal precedes a rising edge of the intermediate clock signal, and a falling edge of the intermediate clock signal precedes a falling edge of the input clock signal. The combinational circuit generates a mask clock signal by delaying the intermediate clock signal. The second clock generator generates a transformed clock signal according to the input clock signal and the mask clock signal. The transformed clock signal has two pulses within a cycle of the input clock signal.

A semiconductor device includes a semiconductor substrate including a fin of semiconductor material having a fin width and a fin length. The fin length is greater than the fin width and extends between a first fin end and a second fin end. A gate electrode extends over the fin at a first fin location between the first fin end and the second fin end. A dummy gate electrode extends over the first fin end and is floating.

A semiconductor device includes a semiconductor substrate including a fin of semiconductor material having a fin width and a fin length. The fin length is greater than the fin width and extends between a first fin end and a second fin end. A gate electrode extends over the fin at a first fin location between the first fin end and the second fin end. A dummy gate electrode extends over the first fin end and is floating.

Provided is a memory device for a logic-in-memory. The memory cell includes: a ternary memory cell for storing ternary data: and a weight cell for controlling a current flowing in an operation line on the basis of a weight signal transmitted from the ternary memory cell and an activation signal transmitted via an activation line, wherein the weight cell includes a first transistor for receiving an input of weight data from a first node corresponding to a stored value of the ternary memory cell, a second transistor for receiving an input of inversed weight data from a second node corresponding to an inversed stored value of the ternary memory cell, and a third transistor for receiving an input of an activation signal transmitted via the activation line.

A method for accessing a memory cell includes enabling precharging of a bit line of the memory cell before a next access of the memory cell. The method includes disabling the precharging after a first interval if the next access is a write. The method includes disabling the precharging after a second interval if the next access is a read. The first interval is shorter than the second interval.

A hybrid memory system provides rapid, persistent byte-addressable and block-addressable memory access to a host computer system by providing direct access to a both a volatile byte-addressable memory and a volatile block-addressable memory via the same parallel memory interface. The hybrid memory system also has at least a non-volatile block-addressable memory that allows the system to persist data even through a power-loss state. The hybrid memory system can copy and move data between any of the memories using local memory controllers to free up host system resources for other tasks.

A memory device that is operable at a first voltage domain and a second voltage domain includes a memory array, a power saving mode pin and a word line level shifter circuit. The memory array operates at the first voltage domain. The power saving mode pin is configured to receive a power saving mode enable signal that is at the second voltage domain. The power saving mode enable signal is configured to enable a power saving mode of the memory device. The word line level shifter circuit is coupled to the memory array and the power saving mode pin, and is configured to clamp a word line of the memory array to a predetermined voltage level that corresponds to a first logic state during the power saving mode of the memory device.

A semiconductor structure includes an SRAM cell that includes first and second pull-up (PU) transistors, first and second pull-down (PD) transistors, first and second pass-gate (PG) transistors, and bit line (BL) conductors. The first PU and the first PD transistors form a first inverter. The second PU and the second PD transistors form a second inverter. The first and the second inverters are cross-coupled to form two storage nodes that are coupled to the BL conductors through the first and the second PG transistors. The first and the second PU transistors are formed over an n-type active region over a frontside of the semiconductor structure. The first and the second PD transistors and the first and the second PG transistors are formed over a p-type active region over the frontside of the semiconductor structure. The BL conductors are disposed over a backside of the semiconductor structure.