Apparatuses and techniques are described for programming a multi-tier block in which sub-blocks are arranged in respective tiers. When a program operation involves the source-side sub-block, the NAND strings are pre-charged from the source line. When a program operation involves the drain-side sub-block, the NAND strings are pre-charged from the bit line. When a program operation involves an interior sub-block, the NAND strings can be pre-charged from the bit line if all sub-blocks on the drain side of the interior sub-block are erased, or from the source line if all sub-blocks on the source side of the interior sub-block are erased. A table can be provided which identifies free blocks, free sub-blocks and a corresponding program order. If such a table is not available, the sub-blocks can be read to determine whether they are programmed.

A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to determine that a power loss event has occurred, determine that one or more blocks are in an erased state, examine a block of the one or more blocks to determine whether the block is a SLC erased block or a TLC erased block, and place the block in a SLC pre-erase heap if the block is the SLC erased block or in a TLC pre-erase heap if the block is the TLC erased block. The controller is further configured to determine a first bit count of page0 for a SLC voltage for the block, determine a second bit count of page1 for a TLC voltage for the block, and classify the block as either a SLC erased block or a TLC erased block.

A system includes a memory device including a memory array and control logic, operatively coupled with the memory array, to perform operations including causing an erase operation to be performed. The erase operation includes sub-operations. The operations further include causing defect detection to be performed during at least one sub-operation of the sub-operations. The defect detection is performed using at least one defect detection method with respect to at least one failure point.

An operation method of a nonvolatile memory device which includes a memory block having wordlines includes performing an erase on the memory block, performing a block verification on the memory block by using a 0-th erase verification voltage, performing a delta verification on the memory block by using a first erase verification voltage different from the 0-th erase verification voltage when a result of the block verification indicates a pass, and outputting information about an erase result of the memory block based on the result of the block verification or a result of the delta verification. The delta verification includes generating delta counting values respectively corresponding to wordline groups by using the first erase verification voltage, generating a delta value based on the delta counting values, and comparing the delta value and a first reference value.

A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines and bit lines and arranged in strings and configured to retain a threshold voltage. Each of the memory cells is configured to be erased in an erase operation occurring during an erase time period. A control circuit is configured to adjust at least a portion of the erase time period in response to determining the erase operation is a segmented erase operation and is resumed after being suspended. The control circuit applies an erase signal having a plurality of voltage segments temporally separated from one another during the erase time period to each of the strings while simultaneously applying a word line erase voltage to selected ones of the word lines to encourage erasing of the memory cells coupled to the selected ones of the word lines in the segmented erase operation.

A non-volatile memory device, including a non-volatile memory cell array, a sense amplifier, a random access memory (RAM), and a buffer circuit, is provided. The sense amplifier is configured to generate readout data. The RAM is configured to store write-in data. The buffer circuit generates a detection result according to target data and the readout data, and writes the detection result to the RAM.

A memory device includes a cell area including memory blocks, and a peripheral circuit area including peripheral circuits that execute an erase operation for each of the memory blocks. Each memory block includes word lines that are stacked on a substrate, channel structures penetrate through the word lines, and a source region that is disposed on the substrate and connected to the channel structures. During the erase operation in which an erase voltage is provided to the source region of a target memory block among the memory blocks, the peripheral circuits reduce a voltage of a first word line from a first bias voltage to a second bias voltage at a first time, and to reduce a voltage of a second word line, different from the first word line, from a third bias voltage to a fourth bias voltage at a second time different from the first time.

A page buffer circuit includes an intermediate circuit, a data storage circuit and an enhancive circuit. The intermediate circuit is coupled to a bit line coupled to a memory region and configured to form apply a voltage having a voltage level, corresponding to a status of the memory region, to a sensing node. The data storage circuit is configured to store, therein, a value that corresponds to the status of the memory region in response to the voltage level. The enhancive circuit is coupled to the sensing node and configured to increase a capacitance of the sensing node in an enhancive interval during a selected operation.

Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks. In one example, a method is disclosed of testing a plurality of non-volatile memory cells in an array of non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bit line, and wherein each word line is selectively coupled to a row decoder and each bit line is selectively coupled to a column decoder, the method comprising asserting, by the row decoder, all word lines in the array; asserting, by the column decoder, all bit lines in the array; performing a deep programming operation on the array of non-volatile memory cells; and measuring a total current received from the bit lines.

A non-volatile memory device includes a plurality of cell strings in a vertical direction, each of the plurality of cell strings including a plurality of memory cells respectively connected to a plurality of word lines, and an erase control transistor having a first end connected to at least one of both ends of plurality of memory cells and a second end connected to at least one of both ends of each of the plurality of cell strings, and a row decoder configured to apply a first bias voltage to the plurality of word lines in a first period in which an erase voltage applied to the second end of the erase control transistor increases to a target level and to apply a second bias voltage higher than the first bias voltage to at least some of the plurality of word lines in a second period after the first period.